720290Novel, next generation memory for mobile devicesClosedGRD Development of PrototypeInnovate UKThis project aims to develop low power, working samples of CMOS memory ‘chips’ suitable for customer evaluation to prove the viability of SureCore’s novel architecture and circuit designs on a next generation, Fully Depleted Silicon-On-Insulator(FD-SOI) 28nm process technology. SureCore’s design will consume 40% less power than alternative solutions. Today’s smart phones, tablets and MP3 players are possible though System-on-Chip (SoC) devices which integrate much of their functionality. These devices rely on ‘Moore’s Law’ to cram more and more transistors onto a single silicon chip. Static Random Access Memory (SRAMs) can occupy over half the silicon area of a modern SoC and consume up to 70% of battery power. Quantum and atomistic effects are now influencing transistor characteristics reducing product yield and reliability; SRAM designs are particularly sensitive to these effects. Fundamental changes to the underlying transistor structures such as FD-SOI have been developed but cannot be easily adopted into existing design methodologies. SureCore recognise this challenge and through combining device physics knowledge with architecture and circuit design experience, they have developed a novel low power SRAM architecture. Simulation results indicate a power saving of 40%. This project will develop prototype silicon to prove the simulation results are accurate. SureCore can then sell these memory designs to the fabless semiconductor industry.