<?xml version="1.0" encoding="UTF-8"?><ns2:project xmlns:ns1="http://gtr.rcuk.ac.uk/gtr/api" xmlns:ns2="http://gtr.rcuk.ac.uk/gtr/api/project" xmlns:ns3="http://gtr.rcuk.ac.uk/gtr/api/fund" xmlns:ns4="http://gtr.rcuk.ac.uk/gtr/api/person" xmlns:ns5="http://gtr.rcuk.ac.uk/gtr/api/project/outcome" xmlns:ns6="http://gtr.rcuk.ac.uk/gtr/api/organisation" ns1:created="2026-07-08T08:44:08Z" ns1:href="http://gtr.ukri.org/gtr/api/projects/34AA62BD-4823-4551-86FE-06DFB8958F21" ns1:id="34AA62BD-4823-4551-86FE-06DFB8958F21"><ns1:links><ns1:link ns1:href="http://gtr.ukri.org/gtr/api/persons/C29DF2C0-D03C-4719-B528-90ED0C8E0BDA" ns1:rel="PM_PER"/><ns1:link ns1:href="http://gtr.ukri.org/gtr/api/organisations/6FE89559-36A7-4F19-849A-3EB9F8B71C34" ns1:rel="LEAD_ORG"/><ns1:link ns1:href="http://gtr.ukri.org/gtr/api/organisations/6FE89559-36A7-4F19-849A-3EB9F8B71C34" ns1:rel="PARTICIPANT_ORG"/><ns1:link ns1:href="http://gtr.ukri.org/gtr/api/organisations/18802915-D4E5-43B7-A84F-2482C540976C" ns1:rel="PARTICIPANT_ORG"/><ns1:link ns1:end="2017-11-30T00:00:00Z" ns1:href="http://gtr.ukri.org/gtr/api/funds/A5CDF640-AA8E-48C5-B0CF-D53857164940" ns1:rel="FUND" ns1:start="2015-05-31T23:00:00Z"/></ns1:links><ns2:identifiers><ns2:identifier ns2:type="RCUK">102262</ns2:identifier></ns2:identifiers><ns2:title>Expanding and Improving Adiabatic Logic in the eSi-RISC CPU</ns2:title><ns2:status>Closed</ns2:status><ns2:grantCategory>Collaborative R&amp;D</ns2:grantCategory><ns2:leadFunder>Innovate UK</ns2:leadFunder><ns2:abstractText>Static CMOS circuit design is ubiquitous in digital ASICs and SoCs, and is preferred over other logic families due to its low power consumption. However, power consumption is still a problem for many battery powered devices using static logic and the problem of dark silicon is predicted as CMOS scaling continues. An alternative, yet commercially unexploited circuit design style is adiabatic logic, which has been shown to demonstrate up to an order of magnitude lower power consumption. This project will be to implement the main components of a commercial CPU using adiabatic logic across a range of IC processes.</ns2:abstractText></ns2:project>