131664High deposition rate superfill copperClosedFeasibility StudiesInnovate UK3-D Integrated circuits, utilizing vertical metal inter die connections, will ultimately provide improved system performance, smaller form factor and reduced cost when compared to current largely 2-D device formats. They enable the stacking of homogeneous or hetrogenous devices in a small package which in turn will opens up many new applications. Currently the cost associated with the fabrication of the vertical Cu connections called Through Silicon Vias (TSVs) is limiting the adoption of this technology. Appoximately 50% of the cost of the formation of an advanced TSV is associated with the Electrochemical Deposition (ECD) of Cu and the field Cu removal step. We aim to substantially increase (>2x) the deposition rate of the ECD Cu by improving the transport kinetics within the high aspect ratio vias. Cost reductions achieved by this advance will help make TSV accessable for more applications.