10121665Cryogenic Qualification of CMOS logic & memory to enable Quantum Computer scaling.ClosedCollaborative R&DInnovate UKWith the advent of AI an ever-increasing amount of energy is required for computing. Moore's law is slowing as circuit dimensions approach physical limits. Quantum computers can create a computational space much larger than their classical counterparts. They will shape computing, science and commercial standards by solving numerical problems that are currently out of reach in fields including chemistry, material science, logistics, machine learning and cryptography. The race is on to build the world's first practical quantum computers, which requires scaling from arrays of a few dozen qubits to thousands and then on to millions of qubits. To achieve this we need to create integrated systems of qubit arrays and control electronics. In most implementations, the qubits require cryogenic cooling, typically to a fraction of a degree above absolute zero. Yet conventional silicon chips are designed to operate at room temperature, and if these chips are cooled to cryogenic temperatures, the operating characteristics of the transistors change markedly, and they no longer work as intended. We are working in a consortium of UK Quantum Technology experts to develop new cryogenic transistor simulation models, and based on these, a range of cryogenic CMOS memories. These will allow Quantum Computer developers to design custom cryogenic control chips and thus migrate their room temperature control electronics into the cryostat with the qubits themselves thereby accelerating their scaling potential. SureCore is an expert in the field of low power memory design with demonstrated power savings of up to 50%. In chip design memory is an essential building block storing both program code as well as the data captured from external sources to be processed. Careful management of power dissipation within the cryostat is critical, hence the importance of utilising low power solutions. To validate these memories, we have developed a test chip integrating various sizes/configurations of the memory types with sureCore's proven verification architecture. This utilises Built-In-Self-Test and a custom designed evaluation system to test memories across a range of operating voltages and speeds. Proving they work at cryogenic temperatures, as well as demonstrating that their power and timing performance meet expectations, is critical to ensure market acceptance. This A4I project will address a range of cryogenic test challenges. These include the housing of the test chip in a cryogenic chamber at 4K whilst remotely connected to the evaluation system, external to the chamber, which is responsible for driving various tests and monitoring responses.