10109482MARGE- Mignon Automated Hardware Generation for Embedded Machine Learning ApplicationsClosedLaunchpadInnovate UKThe Digital Economy will ultimately see billions (potentially trillions) of cameras and sensors- so-called 'edge' devices- deployed to record images for security and collect data about: people's health; industrial processes; weather; pollution; traffic levels, amongst many others. Processing this data into information to provide useful insights will require ever-increasing amounts of computing power or network bandwidth to connect edge devices to data processing centres. New computing architectures are thus needed for edge devices to enable the digital economy to deliver its potential improvements to human health and wellbeing, the environment and the economy. Mignon, a Newcastle University spin out, are commercialising such an architecture, called a Tsetlin Machine. This is a machine learning approach driven by propositional logic and characterised by low complexity. Compared to conventional machine learning, it uses up to 10,000 times less power, with 1,000 times less latency. Mignon have demonstrated this using SRAM chips fabricated at 65nm node, trained to recognise characters (MNIST database). Alongside this, Pragmatic has developed a revolutionary semiconductor technology based on metal-oxide thin film transistors (TFTs) to create Flexible Integrated Circuits (FlexICs) fabricated on flexible substrates (e.g., polyimide). This approach cuts production times from months to days, typically at a fraction of the cost of Silicon ICs, and with 1,000 times lower environmental footprint than conventional Silicon fabs. In this project, Mignon will develop tools to automate hardware design, incorporating their Tsetlin Machine. This will automatically design hardware, based on end users with health, environmental or industrial manufacturing datasets. End users will be able to specify if they require processor speed or low power consumption. The project will first demonstrate training and inference capability using in-memory architecture, fabricated at 28nm node as an embedded silicon application, trained using the CIFAR-10 image classification dataset, at Newcastle University. We will then demonstrate that the tool can design TM inference hardware trained by a dataset of ECG samples and recognise atrial fibrillation events, as a representative example. The hardware will be fabricated as a FlexIC to serve as a useful demonstrator to engage end users and customers across economic sectors.