📣 Try out the NEW Gateway to Research and let us know what you think.

We're looking for users to test the new service during August and September and share their feedback. Express your interest by completing this short form.

C 3 D: Mitigating the NUMA bottleneck via coherent DRAM caches (2016)

First Author: Huang C

Attributed to: C3: Scalable & Verified Shared Memory via Consistency-directed Cache Coherence funded by EPSRC

Abstract

No abstract provided

Bibliographic Information

Digital Object Identifier: http://dx.doi.org/10.1109/micro.2016.7783739

Publication URI: http://dx.doi.org/10.1109/micro.2016.7783739

Type: Conference/Paper/Proceeding/Abstract