A High Speed Hardware Scheduler for 1000-Port Optical Packet Switches to Enable Scalable Data Centers (2017)
Attributed to:
Breaking the Copper Bottleneck: Computer Architecture and Power Implications of Photonic Interconnect
funded by
EPSRC
Abstract
No abstract provided
Bibliographic Information
Digital Object Identifier: http://dx.doi.org/10.1109/hoti.2017.22
Publication URI: http://dx.doi.org/10.1109/hoti.2017.22
Type: Conference/Paper/Proceeding/Abstract