Towards zero latency photonic switching in shared memory networks (2014)
Attributed to:
Breaking the Copper Bottleneck: Computer Architecture and Power Implications of Photonic Interconnect
funded by
EPSRC
Abstract
No abstract provided
Bibliographic Information
Digital Object Identifier: http://dx.doi.org/10.1002/cpe.3334
Publication URI: http://dx.doi.org/10.1002/cpe.3334
Type: Journal Article/Review
Parent Publication: Concurrency and Computation: Practice and Experience
Issue: 15