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Impact of interface state trap density on the performance characteristics of different III-V MOSFET architectures (2010)

First Author: Benbakhti B

Attributed to: III-V MOSFETs for Ultimate CMOS funded by EPSRC

Abstract

No abstract provided

Bibliographic Information

Digital Object Identifier: http://dx.doi.org/10.1016/j.microrel.2009.11.017

Publication URI: http://dx.doi.org/10.1016/j.microrel.2009.11.017

Type: Journal Article/Review

Parent Publication: Microelectronics Reliability

Issue: 3