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A EELS Sub Nanometer Investigation of the Dielectric Gate Stack for the Realization of InGaAs Based MOSFET Devices (2009)

First Author: Longo P

Attributed to: III-V MOSFETs for Ultimate CMOS funded by EPSRC

Abstract

No abstract provided

Bibliographic Information

Digital Object Identifier: http://dx.doi.org/10.1017/s1431927609094458

Publication URI: http://dx.doi.org/10.1017/s1431927609094458

Type: Journal Article/Review

Parent Publication: Microscopy and Microanalysis

Issue: S2