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A Variation-Aware Taylor Expansion Diagram-Based Approach for Nano-CMOS Register-Transfer Level Leakage Optimization (2011)

First Author: Banerjee S

Attributed to: Synthesis and Optimisation of Designs Based on Novel Canonical Algebraic Structures funded by EPSRC

Abstract

No abstract provided

Bibliographic Information

Digital Object Identifier: http://dx.doi.org/10.1166/jolpe.2011.1160

Publication URI: http://dx.doi.org/10.1166/jolpe.2011.1160

Type: Journal Article/Review

Parent Publication: Journal of Low Power Electronics

Issue: 4