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1.5 Gbit/s FPGA Implementation of a Fully-Parallel Turbo Decoder Designed for Mission-Critical Machine-Type Communication Applications (2016)

First Author: Li A

Attributed to: Highly-parallel algorithms and architectures for high-throughput wireless receivers funded by EPSRC

Abstract

No abstract provided

Bibliographic Information

Digital Object Identifier: http://dx.doi.org/10.1109/access.2016.2599408

Publication URI: http://dx.doi.org/10.1109/access.2016.2599408

Type: Journal Article/Review

Parent Publication: IEEE Access