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High-Performance FPGA Network Switch Architecture (2020)

First Author: Papaphilippou P

Attributed to: Event-based parallel computing - partially ordered event-triggered systems (POETS) funded by EPSRC

Abstract

No abstract provided

Bibliographic Information

Digital Object Identifier: http://dx.doi.org/10.1145/3373087.3375299

Publication URI: http://dx.doi.org/10.1145/3373087.3375299

Type: Conference/Paper/Proceeding/Abstract