Meeting the design challenges of the nano-CMOS electronics

Lead Research Organisation: University of Southampton

Department Name: School of Electronics and Computer Science

See Joint Proposal E241901

£289,907

Sep 06 - Dec 10

EPSRC

Closed

Research Grant

EP/E002064/1

Mark Zwolinski

Info. & commun. Technol. (100%)

Electronic Devices & Subsys. (35%)

Information & Knowledge Mgmt (25%)

System on Chip (40%)

People	ORCID iD
Mark Zwolinski (Principal Investigator)

Author Name Title

Publication Date Published

10 25 50

Merrett M (2010) Design metrics for RTL level estimation of delay variability due to intradie (random) variations

Campbell Millar (2011) Modelling Circuit Performance Variations Due To Statistical Variability: Monte Carlo Static Timing Analysis

Merrett M (2014) Monte Carlo Static Timing Analysis with statistical sampling in Microelectronics Reliability

Yangang Wang (2010) Statistical power analysis for nanoscale CMOS


Description	How to abstract device-level variability up to logic-level design techniques. Heavy use was made of eScience methodologies.
Exploitation Route	See exploitation routes. Estimations of systems behaviour in the presence of variability have tended to be overly pessimistic. By showing how correlated and uncorrelated variability can be better modelled, the degree of pessimism is much reduced. Hence this is of significant interest to the integrated circuit design community. There is also interest from design tool vendors.
Sectors	Energy


Description	This was part of a larger project involving 5 universities. The contribution from Southampton hasn't led to any direct impact, although we have looked again at some of the ideas for use in other applications.