Self-Timed Event Processor

Lead Research Organisation: Newcastle University
Department Name: Electrical, Electronic & Computer Eng


The field of this research is the design, synthesis and verification of asynchronous and reactive event handling and processing hardware. This hardware is expected to work in an environment of concurrent, distributed, and real-time computation networks. These networks include both truly distributed systems such as wireless networking, sensor networks, and real-time networks as well as highly integrated on-chip networked computers with distributed processing. These systems are becoming more complex, and the traffic among the processing elements is increasing. Therefore handling the events which make up the traffic may determine much of the system performance and characteristics. Both asynchrony and non-determinism are inevitable for computation networks in the future, firstly because of the different timing requirements of different and diverse functional elements. Secondly, concurrent and distributed system implementations lead to greater asynchrony and non-determinism as semiconductor technology advances and the degree of integration increases (the International Technology Roadmap for Semiconductors (ITRS-05) Design document emphasizes multiple clock domains and source-synchronous signalling, and predicts networks of self-timed blocks). Existing methods of designing event-handling systems in hardware are rather ad hoc and have no systematic modelling and synthesis support.From this point of view, the project proposed here may have a major impact on the industrial as well as academic community. We aim to develop a design and synthesis method for self-timed hardware subsystems (called self-timed event processors or STEPs). STEPs will handle events arriving asynchronously and non-deterministically from multiple sources, and respond (such as by allocating resources, whose availability may also be asynchronously and non-deterministically changing) according to user specifications. Self-timing is in the sense that the triggering information is derived from the signals representing the events themselves, and STEPs may be used to form virtual self-timed reactive service blocks with off the shelf service IP cores such as processors or communications devices. We propose that this method will include a general STEP architecture, techniques for deriving wire delay aware designs for the integral parts of the architecture, and techniques for verifying such designs. A general mathematical modelling technique for STEPs at all levels of detail based on Petri nets will form the basis for the design/synthesis and verification work. We aim to develop the design and synthesis techniques to a degree where the process becomes systematic, highly algorithmic, and potentially automatic, and will cover all levels of detail down to hardware gate level schematics. It is our view that STEP technology will be a step forward in the event handling front, and will help towards the realization of systems of self-timed blocks envisioned in ITRS-05.The project will involve as a collaborator MBDA UK Ltd, a leading European privider of design technology for real-time distributed systems for missile control. The company has pioneered the Butler (awarded with The Queed's Award for Enterpise 2004) and Route-Table technologies, which provide stimulating starting ideas for STEP, such as tiled circuit architecture.


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Description MThe development of Conditional Partial Order Graphs (CPOGs) is a significant advancement in the formal modelling of microcontrol circuits for specification and synthesis purposes. It is especially beneficial for a class of systems with many behavioural scenarios defined on the same set of
primitive events or actions, which includes event processors. As a result of this work several synthesis, verification, optimisation and mapping tools have been developed to facilitate specification and synthesis of microcontrollers using the proposed methodology. The tools have been successfully incorporated into the Workcraft framework for visualisation and simulation support.

A central topic of this project was low power event processors. In this area, extensive investigations were carried out at all levels of abstraction. These include architectural explorations and analyses using Petri net and Matlab discrete models, detailed studies on the central accumulate and fire
method, detailed designs of accumulate and fire components and further explorations on extending the use of the accumulate and fire concept Network on Chip fault monitoring. One important work
covers the modelling and analysis of power and latency in systems where tasks are managed through accumulate and fire, exposing power and latency tradeoffs. Accumulate and fire as an event response technique was demonstrated to be an effective and efficient method to manage power, latency, and other important properties such as faults.
Exploitation Route Through the use of theoretical methods published and highlighted at:
and the tools under Workcraft,
Sectors Digital/Communication/Information Technologies (including Software),Electronics