C3D: Communication Centric Computer Design

Lead Research Organisation: University of Cambridge
Department Name: Computer Laboratory

Abstract

We are at a pivotal point in the design of computational devices.Technology scaling favours transistors over wires which has moved usinto an era where communication takes more time and consumes morepower than the computation itself. We believe that this technologydriver inextricably pushes us toward a communication-centric approachto computer system design from both hardware and softwareperspectives. This grant application is focused on exploring this newcommunication-centric view of computer system design from engineeringwires through computer architecture, compiler design, language designand application mapping. It is our wish that this grant form aportfolio of projects tackling future computational systems involvingthousands of power efficient processors.Communication-centric design can be viewed at several levels ofabstraction:Level 0 - implementation technology, where we will focus oncommunication networks-on-chip.Level 1 - computer architecture, focusing on optimisation ofcommunication flows in the system.Level 2 - algorithm mapping to allow automated placement of data andcode across a manycore computing surface.Level 3 - programming language and compiler design to allowparallelism and locality to be easily expressed.An FPGA based simulation infrastructure will also be constructed toallow research results to be obtained from hardware work at levels 0and 1, and to efficiently support software research undertaken atlevels 2 and 3.

Publications

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Audzevich Y (2014) Power Optimized Transceivers for Future Switched Networks in IEEE Transactions on Very Large Scale Integration (VLSI) Systems

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Banerjee A (2009) An Energy and Performance Exploration of Network-on-Chip Architectures in IEEE Transactions on Very Large Scale Integration (VLSI) Systems

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D Greenfield (2009) Implications of Electronics Technology Trends to Algorithm Design in The Computer Journal

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Watts P (2012) Energy Implications of Photonic Networks With Speculative Transmission in Journal of Optical Communications and Networking

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Zaidi A (2016) Value State Flow Graph A Dataflow Compiler IR for Accelerating Control-Intensive Code in Spatial Hardware in ACM Transactions on Reconfigurable Technology and Systems

 
Description Motivated by electronics technology scaling favoring transistors rather
than wires, this project explored communication scaling issues for future
computer systems. Daniel Greenfield (PhD) undertook a more theoretical
study exploring communication in computer hardware, software and even
mammalian brains. His Ph.D. thesis won the 2011 BCS/CPCC Distinguished
Dissertation Award for the best Ph.D. thesis in Computer Science in the
UK. Dynamic algorithm scheduling was explored by Milos Puzovic (PhD).
Gregory Chadwick (PhD) explored explicit communication mechanisms in
multithreaded and multicore processors by prototyping such systems with
assistance from two short-term RAs (Saar Drimer and Theo Markettos).
Locality aware computer architecture was explored by Daniel Bates (Ph.D.
half funded from this project). Chris Fensch (RA) and Nick
Barrow-Williams (Ph.D. student funded from another source) explored
communication optimisations for cache coherent systems by exploiting
physical locality. Ali Ziedi (Ph.D.) explored communication in algorithms
and efficient mappings onto reconfigurable hardware. Arnab Banerjee (RA)
explored dynamic communication hardware mechanisms and their power
implications.

In terms of the original objectives:

1. Gregory Chadwick, Saar Drimer and Theo Markettos completed this objective to creation a hardware+software infrastructure to enable manycore parallel computer architectures to be simulated in detail in real time. This resulted in a multithreaded processor (Mamba) and associated FPGA infrastructure.

2. Gregory Chadwick, Chris Fensch and Nick Barrow-Williams completed the investigation of many core architectures. A new multithreaded processor (Mamba) was produced. New locality aware cache coherency mechanisms were investigated. Both lead to publications and two Ph.D. thesies.

3. Ali Ziedi explored language design and compilation issues for manycore systems resulting in a Ph.D. thesis.

4. Arnab Banerjee explored reconfigurable networks-on-chip for manycore systems resulting in an IEEE journal paper.

5. Milos Puzovic explored algorithm mapping techniques for manycore resulting in a Ph.D. thesis.

In addition, more theoretical underpinnings were undertaken by Dan Greenfield resulting in publications, a Ph.D. thesis and the Distinguished Dissertation award.
Exploitation Route The work linking communication scaling in brains and chips provides a nice link between electronics and biology with we and others are exploiting.

Proximity cache coherence is being explored by industry to improve power efficiency for future computer systems.
Sectors Digital/Communication/Information Technologies (including Software),Electronics

 
Description DARPA
Amount £1,947,048 (GBP)
Funding ID FA8750-11-C-0249 
Organisation Defense Advanced Research Projects Agency (DARPA) 
Sector Public
Country United States
Start 10/2011 
End 09/2015
 
Description DARPA
Amount £1,947,048 (GBP)
Funding ID FA8750-11-C-0249 
Organisation Defense Advanced Research Projects Agency (DARPA) 
Sector Public
Country United States
Start 10/2011 
End 09/2015