High permittivity dielectrics on Ge for end of Roadmap application

Lead Research Organisation: University of Liverpool
Department Name: Electrical Engineering and Electronics

Abstract

The semiconductor industry is now driven largely by applications pull for mass market consumer goods and it is essential that circuit performance is continually improved if the insatiable demand for such products is to be satisfied. The continuing miniaturisation of transistors within CMOS circuits or 'chips' results in degradation of transport properties in the Si-based MOS transistor channels resulting in reduced drive current and hence circuit speed. It is also increasingly difficult to engineer transistors wherein the ultra-short channel (10s of nanometre) is controlled exclusively by the gate electrode; so-called 'short channel effects'. To control this latter effect, increasingly thin gate dielectric is required (circa 2nm) but this leads to excessive leakage curent through the gate through the quantum mechanical tunnelling effect. This gate leakage compromises the operation of the transistor and most importantly, gives rise to very considerable power consumption which reduces battery lifetime in portable products, and also contributes to severe heating of the chip. The use of a dielectric with a higher permittivity (k) allows for a thicker gate oxide with much reduced leakage, whilst maintaining the drive current of the transistor.Germanium semiconductor was used for the very first transistors and possesses excellent transport properties, far superior to those of Si. The successful integration of hafnia based dielectrics for the MOS gate stack, first by Intel, closely followed by other major companies, has been instrumental in installing a new radicalism into the industry. Thus there is now considerable interest incorporating a Ge pMOST and either Ge or a III/V material for the nMOST within CMOS gates. The disadvantage of the lack of a good native oxide for the case of Ge is now mitigated by the availability and proven nature of deposited dielectrics. The combination of a high mobility channel made in Ge, and a reliable hi-k gate dielectric, is highly desirable. The central aim of this project then is to advance the knowledge and underlying science of Ge MOSFETs, crucially in the area of the gate stack. In particular, rare-earth dielectrics on Ge offer the possibility of a 'magic bullet' solution: a fully scaleable gate stack on a high mobility channel, to the end of the CMOS road map dictated by 'Moore's Law.' Hafnia-based gate stacks are at a more advanced stage in the field but require an interfacial layer which calls for further study into the stability of the native oxide (GeO2) and a technological solution for surface passivation. The 'k' can be increased by doping of the hafnia. There is a pressing need to understand the physics underlying the turn-on or threshold voltage of Ge transistors, which is affected by parasitic 'acceptor-like' energy states near the valence band edge and hence find an engineering solution. New measurement techniques need to be developed to assess phenomena peculiar to Ge devices. Furthermore, the reliability has hardly been looked at for Ge oxide stacks. There are certainly a radically different set of issues compared to Si which will have, in turn, an impact on the suitable materials in the gate stack. Interface states near the conduction band edge are thought to be responsible for the low electron mobility which is proving a 'killer' for the nMOST. These technological challenges will be addressed in this project, by a team who have individually and collaboratively, had active participation in dielectrics research over a period of decades. The team cover the subject from atomistic level theory and modelling, through screening of novel materials and chemical precursors, growth and deposition, fabrication, physical and electronic characterisation; to reliability testing. The group members have very strong links into industry and research institutions along this chain of expertise.

Planned Impact

The project team envisages the development of new manufacturing process steps for CMOS technologies beyond the 22nm node, with proven reliability. The application of atomic layer deposition (ALD) for the manufacture of a high-k dielectrics for germanium-based semiconductor devices, constitutes a potential, significant advance in this field. The innovations arising from this project are essentially three-fold. Firstly, ALD technology is being extensively developed for the microelectronics industry and for flat panel display products. This project will exploit the ability of ALD for control of the germanium - dielectric interface and for the subsequent high-k deposition. It is envisaged that ultimately the ALD high-k process will deliver a CMOS process suitable for the next generations of processor devices. SAFC Hitech will receive direct benefit from the outcomes of the research as will Umicore who supply Ge wafers to the industry. Secondly, the project has the potential to develop new precursor materials, specifically tailored for germanium-based electronic devices. The drivers here are cost reduction; precursor shelf life and ease of handling; useful yield; and recycling of waste. The precursors will also have the potential for 'spill-over' applications from the Electronics Industry to others which requires advances in both conductive and dielectric thin film materials. These precursors will have applications in other market sectors across the broader field of thin film nanotechnolgy. The specific applications where hi-permittivity dielectrics can make a major impact are as follows: photovoltaics, catalysts, plastic electronics, high precision passive components for system-on-chip with applications rf, low power electronics and medical electronics; high value 'super capacitors' for storage in energy harvesting systems (no battery electronics) and others. Thirdly, the team can also foresee a major contribution and impact into the underlying reliability science which will provide the ultimate benchmark for these new materials. The results will therefore be demonstrably 'technologically relevant'. IMEC are a world leading Research Institute providing research and development ahead of industrial needs by 3 to 10 years, in nanoelectronics, nanotechnology, design methods and technologies for ICT systems. They provide a gateway into major international semiconductor companies, providing the possibility to greatly enhance the technological and scientific impact of the research. Finally, the multi-disciplinary nature of the project will provide a superb training environment for young scientists employed on the project, extending from fundamental modelling and growth science through to devices. The research will receive wide dissemination through a broad range of conferences and workshops which have high levels of industrial participation.
 
Description The Liverpool group contributed to three routes of Ge interface engineering for adoption in CMOS technology: (i) the use of high-? materials that are intimate with Ge, such as La2O3 and Y2O3, (ii) the introduction of a robust ultra-thin high-? interfacial layer barrier, such as Al2O3 or Tm2O3, and (iii) sulphur passivation using ALD HfO2, Al2O3 and HfTiO.
Exploitation Route Rare-earth oxides inclusion as interfacial layers seem as viable solution for Ge interface engineering. Furthermore, Liverpool group contributed to reliable measurement methods to determine band offsets for the incessant development of nanoelectronics.
Sectors Education,Electronics

 
Description EPSRC Global Challenges Research Fund (GCRF) Award 2016, Digital in India
Amount £33,900 (GBP)
Funding ID EP/P510981/1 
Organisation Engineering and Physical Sciences Research Council (EPSRC) 
Sector Academic/University
Country United Kingdom
Start 08/2016 
End 03/2017
 
Description The European Union 7th framework programme under grant agreement 312483 - ESTEEM2
Amount € 12,000 (EUR)
Organisation European Union 
Sector Public
Country European Union (EU)
Start 10/2015 
End 10/2016
 
Description The European Union 7th framework programme under grant agreement 312483 - ESTEEM2
Amount € 10,000 (EUR)
Organisation European Union 
Sector Public
Country European Union (EU)
Start 02/2013 
End 07/2013
 
Description UKIERI
Amount £41,600 (GBP)
Funding ID 151218 
Organisation British Council 
Sector Charity/Non Profit
Country United Kingdom
Start 04/2018 
End 03/2020
 
Description CEMES-CNRS, France 
Organisation National Center for Scientific Research (Centre National de la Recherche Scientifique CNRS)
Country France 
Sector Public 
PI Contribution Liverpool group correlated studies provided by CNRS-CEMES with in-house physical characterisation results.
Collaborator Contribution CNRS contributed comprehensive HRTEM and EELS studies on selection of high-k gate stacks on germanium.
Impact There has been one invited talk, one journal paper published and two additional journal paper planned. The collaboration is multi-disciplinary and it involves work from areas of surface science, material science, solid-state physics and electronics.
Start Year 2013
 
Description Chalmers 
Organisation Chalmers University of Technology
Country Sweden 
Sector Academic/University 
PI Contribution Joint papers and discussions
Collaborator Contribution Joint papers and discussions
Impact Raeissi B, Piscator J, Engström O, Hall S, Buiu O, Lemme MC, Gottlob HDB, Hurley PK, Cherkaoui K, Osten HJ, 'High-k-oxide/silicon interfaces characterized by capacitance frequency spectroscopy.' Solid-State Electronics, 52, pp. 1274-1279 (2008) Gottlob HDB, Schmidt M, Lemme MC, Kurz H), Mitrovic IZ, Werner M, Davey WM, Hall S, Chalker PR, (Cherkaoui K, Hurley PK, Raeissi B, Engström O, and SB Newcomb), 'Gd silicate: A High-k Dielectric Compatible with High Temperature Annealing.' Jnl. Vac. Sci. & Technol. B, Vol. 27(1), pp.249-252 (2008) Raeissi B, Piscator J, Engström O, Hall S, Buiu O, Lemme MC, Gottlob HDB, Hurley PK, Cherkaoui K, Osten HJ, 'High-k-oxide/silicon interfaces characterized by capacitance frequency spectroscopy.' Solid-State Electronics, 52, pp. 1274-1279 (2008) Engström O, Raeissi B, Piscator J, Mitrovic IZ, Hall S, Gottlob HDB,Schmidt M, Hurley PK, Cherkaoui K, 'Charging phenomena at the interface between high-k dielectrics and SiOx interlayers.' Jnl. Telecomms. & IT, Vol, 1/2010, 10-19 (2010) Engstrom O, Sedghi N, Mitrovic IZ, Hall S 'Analysis of electron capture at oxide traps by electric field injection.' Appl. Phys. Letts., 102, p. 211604, doi: 10.1063/1.4807845, May (2013) Mitrovic IZ, Hall S, Sedghi N, Simutis G, Dhanak VR, Bailey P, Noakes TCQ, Alexandrou I, Engstrom O,'On the nature of interfaces in ultra-thin TiN/LaLuO3 amorphous molecular beam deposited gate stacks on silicon.' Jnl.Appl.Phys, vol 112, pp. 044102, 1-6, August (2012) Engstrom O, Mitrovic IZ and Hall S, 'Non-abrupt interface between hafnium oxide and its interlayer on silicon.' Solid-State Electronics, Vol.75, pp.63-68 http://dx.doi.org/10.1016/j.sse.2012.04.042 (2012)
 
Description Demokritos, Greece 
Organisation National Centre for Scientific Research (NCSR) Demokritos
Country Greece 
Sector Public 
PI Contribution Liverpool group provided detailed physical characterisation.
Collaborator Contribution NCSR Demokritos deposited by molecular beam epitaxy selection of samples on La2O3, Y2O3, Al2O3 and GeO2 on germanium and provided also electrical characterisation on these gate stacks.
Impact There have been two journal papers from joint work; it is multi-disciplinary across material science, surface science and solid-state electronics.
Start Year 2013
 
Description ENEA, Italy 
Organisation National Agency for New Technologies, Energy and Sustainable Economic Development (ENEA)
Department Frascati Research Centre
Country Italy 
Sector Public 
PI Contribution Correlated obtained results with the measurements at Liverpool.
Collaborator Contribution XPS measurements.
Impact There is a journal paper to be submitted from joint work.
Start Year 2013
 
Description IMEC - REALITY 
Organisation Research Councils UK (RCUK)
Department IMEC - REALITY
Country Belgium 
Sector Multiple 
Start Year 2005
 
Description J.A. Woollam, USA 
Organisation J.A. Woollam
Country United States 
Sector Private 
PI Contribution The results correlated to the ones obtained by Liverpool group.
Collaborator Contribution VUV-VASE measurements in the energy range 0.8-8.5 eV.
Impact Three journal papers published.
Start Year 2012
 
Description KTH, Sweden 
Organisation Royal Institute of Technology
Country Sweden 
Sector Academic/University 
PI Contribution The group at Liverpool provided comprehensive physical characterisation including X-ray photoelectron spectroscopy, variable angle spectroscopic ellipsometry, and X-ray diffraction on samples provided by KTH.
Collaborator Contribution KTH group deposited set of germanium oxide (by thermal oxidation) and thulium oxide (by atomic layer deposition) thin layers on germanium.
Impact There have been two journal papers published from joint work, one invited talk, and further two journal papers planned. The published papers were listed in the 'Publications' section.
Start Year 2012
 
Description LivWiSE Christmas 2015 Lecture 
Form Of Engagement Activity A talk or presentation
Part Of Official Scheme? No
Geographic Reach Local
Primary Audience Other audiences
Results and Impact The 2015 Liverpool Women in Science and Engineering (LivWiSE) Christmas lecture series was a sell out with over 300 people attending. There was a good mixture of school children, University of Liverpool staff, students and members of the public.
One attendee sent the following message after the event:
"Just to say a huge thank you to all the speakers and for organising the event last evening. I attended with my daughter who is in 6th form and wants to do engineering - it was so great for her to see the range of possibilities available and you have such positive role models (in a world where the position of women is so often negatively stereotyped).  The passion of the speakers for their fields really shone through."
Year(s) Of Engagement Activity 2015