DOME: Delaying and Overcoming Microprocessor Errors

Modern day computer systems have benefited from being designed and manufactured using an ever-increasing budget of transistors with very reliable integrated circuits. However, moving forward such a ''free lunch'' is over and forgotten nightmares faced by computer pioneers are coming back to haunt us. Not so long ago, unreliable valves were the basic building blocks for computers and research focussed on how to successfully compute, overcoming this underlying weakness (e.g. von Neuman, 1956, ''Probabilistic logics and the synthesis of reliable organisms from unreliable components'').

State-of-the-art integrated circuit technologies have now reached the range of 40-22 nanometers, posing significant reliability challenges. Hard or permanent errors can manifest themselves at any point during a processor's lifetime. During manufacturing, errors can render a proportion of a chip incapable of computing, thus decreasing yield and profit.
As we move towards smaller and smaller components, transistors take less and less time to wearout, becoming more prone to failure in the field. Traditional reliability solutions involve applying high-cost redundancy to the hardware structures within the processor, providing backup spares for when errors occur. On the application side, solutions also involve redundancy by running multiple copies of each piece of software.

A common criticism of current reliability solutions is that they do not consider how the software and hardware can be co-designed synergistically to tackle this challenge. Redesigning and reimplementing general purpose software applications will incur an unaffordable price tag. Our hypothesis is that virtualization technologies (a layer that transparently hides the underlying platform from the application software) have an important role to play. In particular, managed runtime environments (MREs) have become pervasive for high-productivity software developers and represent a promising vehicle for providing reliability mechanisms. Within these systems, applications can be monitored and morphed without user intervention.

There are two complementary strands to our proposed research, focused around a co-designed MRE and multicore computer architecture. Firstly, we will consider wearout mitigation schemes to slow processor ageing and lengthen a chip's lifetime before a hard fault occurs. Secondly, given that an error will occur at some point during a system's life, we will develop error-tolerance approaches that maintain execution on faulty hardware.

If successful, we believe this project will be seen as a significant milestone in the development of wearout-conscious and error-tolerant multicore architectures over the next decade. This research programme will advance our understanding of the field, tackling the UK Microelectronics Grand Challenge of Moore for Less that has been signposted by EPSRC. It is also important to highlight that this proposal tackles a key aspect of the new EPSRC ICT capability priority on "Many-core architectures and concurrency in distributed and embedded systems".

State-of-the-art integrated circuit technologies have now reached the range of 45-22 nanometres, posing significant reliability challenges. Moving forward, multicore and many-core chips reliability is as a key design challenge for systems designers. DOME, our proposed research program, provides a transparent path forward for software applications. Managed runtime environments (MREs) have become pervasive for high-productivity software developers and represent a promising virtualisation vehicle for providing reliability mechanisms. Within these systems, applications can be monitored and morphed without application developer intervention.

Our objectives are focused around a co-designed MRE and computer architecture for multicore chips. We will consider wearout mitigation schemes to slow processor ageing and lengthen a chip's lifetime before a hard fault occurs. Given that an error will occur at some point during a system's life, we will develop error-tolerance approaches that maintain execution on faulty hardware.

If successful, we believe this project will be seen as a significant milestone in the development of wearout-conscious and error-tolerant multicore architectures over the next decade. This research programme will advance our understanding of the field, tackling the UK Microelectronics Grand Challenge of Moore for Less that has been signposted by EPSRC.

The main beneficiaries of this work can be broadly categorised into two groups. Firstly, academics stand to benefit through the development of our ideas into working prototypes. We are aiming to restructure software on-the-fly to adapt to changes in the underlying system's reliability. This is something that has never been done before and, if successful, will open up a new research area of dynamic optimisation for reliability.

The second group of beneficiaries is industry. We have secured strong letters of support from major companies, such as UK-based ARM, Microsoft and Qualcomm. They testify that our proposed research is both necessary to address the upcoming challenges that they face, and it also outlines novel solutions to the problems. Interactions with UK industry will allow our ideas to be fed into their research and development efforts in this area.

Furthermore, alongside the activities described above, at an early stage in the project we intend to identify the core IP generated from the research. With this in hand, we will evaluate the potential for further economic gain. Both universities have an excellent track record in commercial exploitation, Silistix and Transitive being two such examples.

As with any long-term research, it is complex to express its impact on the wider research community and society. However, EPSRC's vision for a digital economy is underpinned by the need for reliable electronics and systems. This proposal will significantly contribute towards this goal. Similarly, DOME will provide contribute towards the new EPSRC ICT capability theme on "many-core architectures and concurrency in distributed and embedded systems".