Energy Proportional Computing With Heterogeneous and Reconfigurable Processors (ENPOWER)

Energy efficiency is one of the primary design constraints for modern processing systems. Limited battery life and excessive internal power densities limit the number of transistors that can be active simultaneous in a silicon chip. Energy and power reduction in conventional computing is limited by the inability of modifying the architecture or adapting to changes in the fabrication process, temperature or application requirements after chip fabrication. When these changes are possible are limited by the need of "margining" that introduces safety margins so devices operate under worst conditions. Worst conditions are rarely the case an important energy and performance gains are possible if technology can adapt to the real conditions of operation. This research addresses this challenge by investigating energy proportional computing with a novel voltage, frequency and logic scaling triplet to adapt to changes in applications, fabrication or operating conditions. The results from this research are expected to deliver new fundamental insights to the question of: How future computers can obtain orders of magnitude higher performance with limited energy budgets?

The potential beneficiaries of this research are the electronics and semiconductor companies involved in the creation of the multi-core processing platforms that will be at the centre of future super-computing devices. A good indication of the challenges that this industry faces over the next 20 years is available in the International Technology Roadmap for Semiconductors (ITRS). This report identified energy as a fundamental challenge that future integrated circuits will face. It is expected that the process variability in deep submicron technologies will make designing chips assuming worst case conditions wasteful and uneconomical.
The objective set by the IRTS in terms of energy requirements is to maintain the static and dynamic power at current or decreasing levels despite the exponential growth in logic complexity and throughput. Self-regulating processing cores able to control their own voltage supplies, activation periods, clock frequencies, active logic etc will be needed since the effects of scaling and variability will add up increasing the problems of power density and leakage. The proposed technology is highly relevant to servers dealing with offline analytics, web applications and large data sets applications in areas, including meteorology, seismic, genomics, complex physics simulations. etc. These applications offer high level of parallelism so that multiple cores can work on the problem at a time but the power requirements of these large collections of server processors becomes very high. Kernel acceleration using FPGA fabrics able to compute at the limit could offer power reductions of orders of magnitude. To make sure that the knowledge and know-how permeates adequately into the industry environment the following actions will be taken:
1. The hardware demonstrators will be presented with a series of visits to the industrial collaborators Qioptiq and Xilinx and other companies working in the areas of interest such as Maxeler and ESA. These visits will be organized at key stages of the project to ensure that adequate feedback is received. Short secondments of academic staff to industry will be arranged together with the visits. Additional contacts will be made with companies developing server systems around ARM technology (e.g. Calxeda) to demonstrate the potential improvements in energy of the approach. The technology could also extend the design flows of companies targeting high-performance computing using FPGAs such as Maxeler. The authors already have a working relationship with Maxeler and this will be used to demonstrate the technology on a Maxeler acceleration system.
2. In the EACO workshops we intend to organise a series of seminars/demonstrations to bring the project in contact with industry and academia. We believe that an interactive demonstration around a multimedia application in the area of video processing should be able to attract plenty of general interest.
3. The traditional avenues of journal and conference publications will be also fully utilized. We have identified conferences such as DATE (Design and Test in Europe), FPL (Field Programmable Logic), DAC (Design Automation Conference) as high quality conferences adequate for this work. Journals such as IEEE TVLSI, IEEE Computers and IET CDT will be targeted.
The expected impacts of this research can be summarised as:
1. To understand how available chips can compute to the limit by tracking the optimal hardware and software configuration.
2. To deliver one order of magnitude better energy/performance operating exploiting a scalability triplet formed by logic, voltage and frequency operating at the limit of reliability.
3. To show how this approach can be applied to high-performance and embedded computing systems used in industrial applications.