Functional Oxide Reconfigurable Technologies (FORTE): A Programme Grant

Lead Research Organisation: University of Southampton
Department Name: Sch of Electronics and Computer Sci

Abstract

Our vision is to rejuvenate modern electronics by developing and enabling a new approach to electronic systems where reconfigurability, scalability, operational flexibility/resilience, power efficiency and cost-effectiveness are combined. This vision will be delivered by breaking out of the large, but comprehensively explored realm of CMOS technology upon which virtually all modern electronics are based; consumer and non-consumer alike.

Introducing novel nanoelectronic components never before used in the technology we all carry around in our phones will introduce new capabilities that have thus far been unattainable due to the limitations of current hardware technology. The resulting improved capability of engineers to squeeze more computational power in ever smaller areas at ever lower power costs will unlock possibilities such as: a) truly pervasive Internet-of-Things computing where minute sensors consuming nearly zero power monitor the world around us and inform our choices, b) truly smart implants that within extremely limited power and size budgets can not only interface with the brain, but also process that data in a meaningful way and send the results either onwards to e.g. a doctor, or even feed it back into the brain for further processing, c) radiation-resistant electronics to be deployed in satellites and aeroplanes, civilian and military and improve communication reliability while driving down maintenance costs.

In building this vision, our project will deliver a series of scientific and commercial objectives: i) Developing the foundations of nanoelectronic component (memristive) technologies to the point where it becomes a commercially available option for the general industrial designer. ii) Setting up a fully supported (models, tools, design rules etc.), end-to-end design infrastructure so that anyone with access to industry standard software used for electronics design today may utilise memristive technology in their design. iii) Introduce a new design paradigm where memristive technologies are intimately integrated with traditional analogue and digital circuitry in order to deliver performance unattainable by any in isolation. This includes designing primitive hardware modules that can act as building-blocks for higher level designs, allowing engineers to construct large-scale systems without worrying about the intricate details of memristor operation. iv) Actively foster a community of users, encouraged to explore potential commercial impact and further scientific development stemming from our work whilst feeding back into the project through e.g. collaborations. v) Start early by beginning to commercialise the most mature aspects of the proposed research as soon as possible in order to create jobs in the UK. Vast translational opportunities exist via: a) The direct commercialisation of project outcomes, specifically developed applications (prove in lab, then obtain venture capital funding and commercialise), b) The generation of novel electronic designs (IP / design bureau model; making the UK a global design centre for memristive technology-based electronics) and c) Selling tools developed to help accelerate the project (instrumentation, CAD and supporting software).

Our team (academic and industry) is ideally placed for delivering this disruptive vision that will allow our society to efficiently expand the operational envelope of electronics, enabling its use in formidable environments as well as reuse or re-purpose electronics affordably.

Planned Impact

FORTE is planned for generating impact in: a) knowledge, b) economy, c) society and d) education, delivered over the short (S, <5 years), medium (M, 5-10y) and long (L, 10y+) -terms.

Knowledge: We will introduce a radically innovative way of implementing reconfigurable hardware, based on new ideas from the field of functional oxides (S/M). This will create a very valuable UK-based network that can lead on developing of industry-ready reconfigurable designs (S/M). The network will rely on participant expertise that will be considerably strengthened by this project in a number of areas: i) Understanding of opportunities for reconfiguration - through the interplay between materials, devices and circuit design (S). The partnership with our industrial stakeholders offers unique opportunities for fundamental discoveries, enabling knowledge transfer and amalgamating new knowledge generated through our new hardware set-ups and applications (S/M). ii) Pushing the performance limits of memory devices beyond current state-of-art as well as engineering them for use in commercially available systems (S/M), iii) Developing novel design concepts (RP3-4) and paradigms (RP5) for providing unprecedented application opportunities (S/M), iv) Developing tools for massively accelerating the electrical characterisation of memory technologies (ArC) (S) and v) Forging the link between CMOS and memristive technologies, with advances in circuit/system design (S/M).
Overall, we will be developing end-to-end infrastructure from a range of methods, models, devices, circuits, technologies, design methodologies and practical applications. Our trans-disciplinary approach provides an ideal framework for establishing a wide knowledge-base, covering both fundamental and applied science, that will be useful for equipping young scientists with unique skillsets (PhDs and PDRAs) and creating the necessary critical mass to further develop these disruptive technologies (S/M). We will also translate this breadth of research developments for reshaping taught modules; first within our consortium's host institutions and then more broadly (S).
Economy: Commercial impact is expected to be delivered via: i) Commercialisation of the research tools that will be developed (described above), thus growing the SME participants (S). ii) Generation of reliable ReRAM device models for use with standard industrial CAD software tools (Cadence) (S), which will improve technological capability (ams AG) (M). iii) Creation of a new field of industrial activity, namely reconfigurable hardware platforms (M/L). We aim attracting substantial amounts of inward investment for first creating and then dominating the global market for 'alternative reconfigurable paradigms'. This combined academic/industrial effort will leap-frog current research. This is realistically achievable by delivering convincing demonstrators (RP6) whilst simultaneously achieving sufficient maturation of the underlying technologies (RP1-2).
Society: Societal impact will be delivered through novel applications and policy shaping. Policies will be influenced as our results become available, through the PI's membership of the internationally highly influential ITRS (SRC) body (S). We aspire delivering a platform technology (RP1-2), which will extend support to numerous applications (RP3-6) to be pursued post-project, many by consortium participants themselves (M/L). These will include: i) Healthcare, notably ReRAM-based intelligent neural interfaces (with Galvani Bio/GSK), ii) RADAR applications (THALES), iii) ReRAM for pervasive sensing and safety (LRG), iii) embedded platforms for IoT (ARM, Maxeler, NXP). Great benefits are also anticipated in the use of the proposed technology in autonomous agents that continuously process large number of data and are often constraint in terms of available resources but also their physical location that in some cases entails being embedded in harsh or inaccessible environments.

Publications

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Manouras V (2021) Frequency Response of Metal-Oxide Memristors in IEEE Transactions on Electron Devices

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Messaris I (2018) A Data-Driven Verilog-A ReRAM Model in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

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Michalas L (2018) Electrical characteristics of interfacial barriers at metal-TiO 2 contacts in Journal of Physics D: Applied Physics

 
Title RAEng Chair in Emerging Technologies on AI Hardware, Themis Prodromakis, University of Southampton 
Description Memristive Technologies for Lifelong Learning Embedded AI Hardware (AI MeTLLE) - AI on Chip for Embedding Intelligence everywhere 
Type Of Art Film/Video/Animation 
Year Produced 2020 
Impact Raise awareness and was shown at RAEng Fellows Day 
URL https://www.youtube.com/watch?v=6ylKRrx053I&t=3s
 
Title Revamping Modern Electronics with Memristive Technologies 
Description Revamping Modern Electronics with Memristive Technologies 
Type Of Art Film/Video/Animation 
Year Produced 2019 
Impact Our vision is to rejuvenate modern electronics by developing a new approach to electronic systems where reconfigurability, scalability, operational flexibility/resilience, power efficiency and cost-effectiveness are combined - all enabled by functional-oxide memristors. 
URL https://www.youtube.com/watch?v=ZbcPRcWkOp0
 
Description We have invented a novel design circuit paradigm that fuses analogue and digital technologies. While the well-known mixed-signal paradigm fuses the analogue and digital worlds at signal level - the underlying technologies remain separate. Throughout this work, we demonstrated for the first time how analogue memristors can be fused with digital circuits for enabling energy efficient implementations of analogue reconfigurable gates, essentially introducing a radical new circuit design paradigm.
Exploitation Route This pushes further the discovery envelope for integrated circuits - beyond the current scaling constraints (Moore's law hitting the nanoscale floor) and is thus anticipated that it will allow circuit designers to provide powerful analogue computation at competitive power-savings.
Sectors Aerospace, Defence and Marine,Electronics,Healthcare,Manufacturing, including Industrial Biotechology

URL http://www.forte.ac.uk/
 
Description Artificial Intelligence (AI) is transforming our society, affecting every aspect of our lives. The internet of things like smartphones, smart watches, smart thermostats or connected healthcare monitors makes our lives easier. But to keep up with technological demands, transistors had to get smaller and smaller which in turn increased the price, and have now reached their physical limit, with - for example - the processing chips that power smartphones containing an average of seven billion transistors that are only a few atoms wide. FORTE researchers came up with an answer - the development of an alternative electronics technology nowadays known as Memristors that is both smaller and more energy efficient than transistors. This technology also empowers electronics with the ability to retain data by 'remembering' the amount of charge that has passed through them - similar to the behaviour of synaptic connections in the human brain. Over the past years, FORTE has invented and matured memristive technologies, developed appropriate models and design tools and innovated new circuit concepts that advance the performance of modern electronics. This has led to initial impact, created interest from additional partners who invested in the use of our technologies such as Google and the Defence Science and Technology Laboratory (DSTL), empowered the international chip design community with open-access tools and contributed to the development of commercial products (e.g. ArC Instruments). ArC Instruments - the spinout that accelerates research & development ArC Instruments LTD was established in 2015 to equip researchers in Memristor Research with the in-house-developed memristor array characterisation instruments developed by two FORTE partners. Over 100 copies of the ArC ONE™ memristor characterisation instrument have been sold to laboratories in over 25 countries. By automating time-consuming measurements in Memristor research, the ArC ONE™ instrument has become the standard characterisation instrument of the international memristor research community. The ArC ONE™ instrument has eased the impact of lockdowns by allowing researchers to work remotely from their lab facility, and to set up home laboratories. Consequently, demand for our instrumentation tools surged during the Covid-19 pandemic. FORTE R&D in monolithic memristor chipsets required the upgrade of our handling instrumentation and a much more powerful instrument, ArC TWO™, was developed that is capable of simultaneous array measurements. Since the release of ArC TWO™ in the second half of 2022, the tool is already in use in four laboratories - outside of the original FORTE academic partners. Hardware solutions for graph databases - ASOCA Technologies developed by FORTE have led to the demonstration of novel hardware architectures (ASOCA chip) for associative memories - the ability to learn and remember the relationship between unrelated items. Apart from the direct scientific interest this has generated, ASOCA provides an excellent solution for accelerating Graph Databases (GDBs). Unlike current databases that store data in cumbersome tables, GDBs encode the connections and relationships between data in an easily navigable structure, promising previously unattainable insight into data structures and enabling new AI paradigms (see "hybrid AI"). FORTE's ASOCA chip is shown to reduce average GDB query times by approximately 2-3 orders of magnitude and simultaneously cut associated energy dissipation. This has the potential to impact the GDB industry as a whole both at scale (allowing cleaner Data Centre operations globally) and locally by enabling the previously impossible adoption of GDBs in pocket-sized computers like our phones. The technology has been developed by accessing FORTE's engineering runs and has been patented for future commercial use (Patent Application No. (Greece): 20220101056). Progress so far has allowed the team to proceed towards the commercial translation of ASOCA. A successful Impact Accelerator Account project with Neo4j (global market leader in GDB solutions) as industrial collaborator, led to expressed economical interest in our results. Moreover, Dr Christos Giotis, who is working on commercialising ASOCA, has received an ICURe Explore grant to focus on market exploration before pursuing further capital for an MVP - a product with enough features to attract early customers and validate a product idea early in the product development cycle. FORTE machine-learning accelerator: potential to become the AI hardware of choice FORTE technologies have been leveraged for establishing a machine-learning accelerator block. The accelerator is underpinned by FORTE's memristor technologies and belongs to the general family of memristor-based accelerators. The key idea was based on the observation that when working with memristor technologies, it is frequently the case that system signals naturally "cross domains", i.e. the input might be in the "analogue voltage" domain, but the output will be in the "analogue current" domain. Normally, engineers attempt to avoid any domain crossing, but throughout FORTE we succeeded in testing the hypothesis that if domains are crossed in a cyclical fashion (e.g. A to B to C and back to A) the result is systems with extreme power efficiency. Our results indicate about 10x improvements in power dissipation and 10x speed-ups. This concept now forms one of the UK's candidates for becoming the AI hardware of choice for embedded applications. Investigation in adiabatic circuit attracts DSTL funding FORTE performed an exploratory investigation into "adiabatic circuits" - specifically of the "charge recovery" flavour. The first version of these circuits was conceived through the use of FORTE-based technology in order to implement the synaptic elements of artificial neural networks; the most fundamental elements of modern AI. The hypothesis was that these circuits would dramatically reduce power dissipation in artificial neural networks. These concepts were developed into a fully capacitive version, spawning a new line of investigation - beyond the use of memristive technology. With the capacitive version, we showed that power-saving values of up to 90% became plausible. These results were published in IEEE TCAS [Maheshwari, Sachin, et al. "An Adiabatic Capacitive Artificial Neuron With RRAM-Based Threshold Detection for Energy-Efficient Neuromorphic Computing." IEEE Transactions on Circuits and Systems I: Regular Papers 69.9 (2022): 3512-3525.]. The work gathered attention from DSTL, who subsequently funded a £1M project entitled "Demonstrate Scalability of Charge Recovery Neural Network" allowing the Edinburgh team to translate this novel concept into practical systems for the defence sector. Rollout of FORTE ReRAM memristor technology via Europractice Given one of FORTE's technologies is CMOS, this has enabled several staff and students across the UK to launch their expertise in chip design through several design submissions, attendance of conferences, and cross-institution meetings. Whilst the COVID-19 pandemic played a role, delays in design submissions were also partly due to this learning process. However, this has enabled new ideas and technologies to be studied and implemented within the academic environment. Being able to share this with other institutions via accessible channels is paramount: Imperial College London has engaged with Europractice to discuss the process by which they procure and offer new technologies to its members. Europractice is a consortium of five renowned European research organizations supplying the microelectronics ecosystem to over 600 academic/research institutions, and 100s of spinouts/SMEs with IC prototyping services, system integration solutions, training activities and possibilities for small-volume production. They support over 1,000 IC fabrication runs per annum. The FORTE team discussed the requirements for offering FORTE ReRAM technology, including its product development kit and IPs, as part of its technology offering. The initial feedback confirms that there is an existing customer base interested in the availability of non-volatile memory in BCD (Bipolar-CMOS-DMOS) technology, a need that is currently not being served. FABulous - versatile FGPA open-source framework wins Google and expert recognition FABulous, a versatile FGPA open-source framework developed by FORTE, allowing for customization and reconfigurable architecture research, ties well in with the movement towards open-source hardware. This is substantially supported by industry, for example by Google, which are facilitating an open-source ecosystem for ASIC design and sponsor hundreds of chip tape-outs annually. FORTE were the first in this program to demonstrate a working FPGA with dedicated arithmetic and memory blocks, taking the lead over competing universities, including Princeton University and the University of Utah. The demonstration of FPGA on LinkedIn has been viewed by 6500 experts so far (https://www.linkedin.com/feed/update/urn:li:activity:6968909076655144960/). Further improvement of FABulous is well on track, supported by a joint 400K USD project with Berkeley granted by Google US. One of the Google Shuttle submissions included a non-volatile ReRAM test chip as a first memristor FPGA test platform which is expected to be shipped in Q3/2023. The FABulous work resulted in two papers at the highest-ranked conference on FPGAs: FPGA'21 and FPGA'22. FABulous did not only attract support from Google and was named essential IP in their open hardware initiative, the tool was also used by Universities like Liverpool John Moores and Bristol, the SLAC National Accelerator Laboratory at Stanford University and Fraunhofer IMS at Duisburg Germany. Farshad Khorrami at New York University recently started designing another TSMC 28 chip with FABulous.
First Year Of Impact 2022
Sector Aerospace, Defence and Marine,Digital/Communication/Information Technologies (including Software),Education,Manufacturing, including Industrial Biotechology,Other
Impact Types Economic

 
Description AI Taxonomy, RAEng policy paper
Geographic Reach Multiple continents/international 
Policy Influence Type Implementation circular/rapid advice/letter to e.g. Ministry of Health
URL https://www.southampton.ac.uk/~assets/doc/publicpolicy/82043%20A4%20-%20AI%20Taxonomy%20brief_v4_web...
 
Description Participation in Feasibility study for UK Semiconductor Infrastructure Initiative
Geographic Reach National 
Policy Influence Type Contribution to a national consultation/review
URL https://www.gov.uk/government/news/government-explores-national-initiatives-to-boost-the-british-sem...
 
Description RAEng Roundtable on proposed new UK funding agency, modelled on the US Advanced Research Projects Agency (ARPA)
Geographic Reach National 
Policy Influence Type Contribution to a national consultation/review
 
Description UKRI Closed Roundtable discussion on Next Generation AI
Geographic Reach National 
Policy Influence Type Participation in a guidance/advisory committee
 
Description A capability for patterning beyond-CMOS devices at atomic scale
Amount £3,141,000 (GBP)
Funding ID EP/V054120/1 
Organisation Engineering and Physical Sciences Research Council (EPSRC) 
Sector Public
Country United Kingdom
Start 06/2021 
End 07/2026
 
Description Autonomous NAnotech GRAph Memory (ANAGRAM)
Amount £347,274 (GBP)
Funding ID EP/V008242/1 
Organisation Engineering and Physical Sciences Research Council (EPSRC) 
Sector Public
Country United Kingdom
Start 12/2020 
End 11/2023
 
Description ICURe EXPLORE for Chris Giotis
Amount £35,000 (GBP)
Organisation Innovate UK 
Sector Public
Country United Kingdom
Start 03/2023 
End 05/2023
 
Description Royal Academy of Engineering Chair in Emerging technologies
Amount £2,800,000 (GBP)
Organisation Royal Academy of Engineering 
Sector Charity/Non Profit
Country United Kingdom
Start 12/2019 
End 12/2029
 
Description Royal Society Industry Fellowship
Amount £135,862 (GBP)
Organisation The Royal Society 
Sector Charity/Non Profit
Country United Kingdom
Start 03/2017 
End 04/2021
 
Description SYNCH
Amount € 4,000,000 (EUR)
Organisation EU-T0 
Sector Public
Country European Union (EU)
Start 01/2019 
End 01/2023
 
Description UKRI Centre for Doctoral Training in Machine Intelligence for Nano-electronic Devices and Systems
Amount £5,820,891 (GBP)
Funding ID EP/S024298/1 
Organisation Engineering and Physical Sciences Research Council (EPSRC) 
Sector Public
Country United Kingdom
Start 03/2019 
End 09/2027
 
Title An Electrical Characterisation Methodology for Benchmarking Memristive Device Technologies 
Description The emergence of memristor technologies brings new prospects for modern electronics via enabling novel in-memory computing solutions and energy-efficient and scalable reconfigurable hardware implementations. Several competing memristor technologies have been presented with each bearing distinct performance metrics across multi-bit memory capacity, low-power operation, endurance, retention and stability. Application needs however are constantly driving the push towards higher performance, which necessitates the introduction of a standard benchmarking procedure for fair evaluation across distinct key metrics. Here we present an electrical characterisation methodology that amalgamates several testing protocols in an appropriate sequence adapted for memristors benchmarking needs, in a technology-agnostic manner. Our approach is designed to extract information on all aspects of device behaviour, ranging from deciphering underlying physical mechanisms to assessing different aspects of electrical performance and even generating data-driven device-specific models. Importantly, it relies solely on standard electrical characterisation instrumentation that is accessible in most electronics laboratories and can thus serve as an independent tool for understanding and designing new memristive device technologies. 
Type Of Material Physiological assessment or outcome measure 
Year Produced 2019 
Provided To Others? Yes  
Impact Introduced a standard method for benchmarking Memristive Device Technologies 
URL https://www.nature.com/articles/s41598-019-55322-4
 
Title Enabled brain neurons and artificial neurons to communicate with each other 
Description Our research on novel nanoelectronics devices has enabled brain neurons and artificial neurons to communicate with each other. This study has for the first time shown how three key emerging technologies can work together: brain-computer interfaces, artificial neural networks and advanced memory technologies (also known as memristors). The discovery opens the door to further significant developments in neural and artificial intelligence research. 
Type Of Material Physiological assessment or outcome measure 
Year Produced 2020 
Provided To Others? Yes  
Impact This article has picked up a lot of media interest and is ranked 1st of the 55 tracked articles of a similar age in Scientific Reports. We hope that this approach will ignite interest from a range of scientific disciplines and accelerate the pace of innovation and scientific advancement in the field of neural interfaces research. In particular, the ability to seamlessly connect disparate technologies across the globe is a step towards the democratisation of these technologies, removing a significant barrier to collaboration. 
URL https://www.nature.com/articles/s41598-020-58831-9
 
Title Memristor Verilog-A model 
Description The translation of emerging application concepts that exploit Resistive Random Access Memory (ReRAM) into large-scale practical systems requires realistic, yet computationally efficient, empirical models that can capture all observed physical devices. Here, we present a Verilog-A ReRAM model built upon experimental routines performed on TiOx-based prototypes. This model was based on custom biasing protocols, specifically designed to reveal device switching rate dependencies on a) bias voltage and b) initial resistive state. Our model is based on the assumption that a stationary switching rate surface m(R,v) exists for sufficiently low voltage stimulation. The proposed model comes in compact form as it is expressed by a simple voltage dependent exponential function multiplied with a voltage and initial resistive state dependent second order polynomial expression, which makes it suitable for fast and/or large-scale simulations. 
Type Of Material Improvements to research infrastructure 
Year Produced 2017 
Provided To Others? Yes  
Impact Enabled the circuits and systems community to innovate novel circuitry and systems. 
URL https://arxiv.org/abs/1703.01167
 
Description Cadence 
Organisation Cadence Design Systems
Country United States 
Sector Private 
PI Contribution Helping Cadence develop tools to meet the ever increasing demand for memory, specifically ReRAM combined with CMOS.
Collaborator Contribution Attended the Annual industrial meeting and provided guidance on the research (how to incorporate our design rules/kits into their standard kits).
Impact We have developed memristor/ReRAM models in Verilog-A formats that can easily be accessed via the Cadence design suite.
Start Year 2018
 
Description GlaxoSmithKline 
Organisation GlaxoSmithKline (GSK)
Country Global 
Sector Private 
PI Contribution Shaping the Bioelectronics agenda. Attended the inaugural Bioelectronics Summit in New York, December 2013. Also our team has directly contributed towards addressing grand challenges of state-of-art neural interfaces related with power consumption and bandwidth requirements that prohibit upscaling above 1,000 channels.
Collaborator Contribution Provided access to data and facilities for in-vitro/-vivo testing at Stevenage.
Impact Lead into the award of a Royal Society Industry Fellowship for translating technology developed through EPSRC funding into Bioelectronic products. Lead to the establishment of neuroLink ltd, a start-up that promotes the use of emerging resistive memory technology (memristors) as efficient computation (on-node processing) elements.
Start Year 2013
 
Description Imperial College London 
Organisation Imperial College London
Country United Kingdom 
Sector Academic/University 
PI Contribution Imperial are a key partner in the Programme grant. We have helped them by providing resources (prototype devices and instruments) as well as hosting the Programme Boards, technical meetings and technical meetings for knowledge exchange.
Collaborator Contribution Imperial have contributed by taking the lead on our 1st Engineering run, providing technical expertise on the IC design. Imperial have used two PhD studentships from the Doctoral College's Training Grant allocation to support the project.
Impact Continued knowledge exchange, leading to the first engineering run for FORTE.
Start Year 2018
 
Description Intel Labs Europe 
Organisation Intel Corporation
Department Intel Ireland
Country Ireland 
Sector Private 
PI Contribution Working with Intel to develop embedded applications and driving innovation in this remit.
Collaborator Contribution Intel have agreed to take part in the advisory meetings, provide technical consultancy for an estimated 30 days over the lifetime of the grant.
Impact TBC
Start Year 2020
 
Description Maxeler 
Organisation Maxeler Technologies Inc
Department Maxeler Technologies
Country United Kingdom 
Sector Private 
PI Contribution Working with Maxeler to improve FPGA computation and reconfiguration capacity on a single die.
Collaborator Contribution Maxeler have agreed to take part in the advisory meetings, provide technical consultancy for an estimated 60 days over the lifetime of the project and offer training on Maxeler development tools, practical data flow development and complex reconfigurable systems design.
Impact TBC
Start Year 2018
 
Description NCSR Demokritos , GREECE- Lima-Chip 
Organisation National Centre for Scientific Research (NCSR) Demokritos
Country Greece 
Sector Academic/University 
PI Contribution Advise PhD students and young researchers on aspects of designing memristor-enabled memories.
Collaborator Contribution Developing scalable Memristor-enabled memories
Impact Two week collaboration visit to NCSR Demokritos in September 2022
Start Year 2022
 
Description NXP 
Organisation NXP Semiconductors was Philips Semiconductor
Country Netherlands 
Sector Private 
PI Contribution Working with NXP to develop embedded applications and driving innovation in this remit.
Collaborator Contribution NXP is providing state of the art MCU development kits and providing the relevant technical support for these products as well as attending our regular review meetings.
Impact TBC
Start Year 2018
 
Description University of Manchester 
Organisation University of Manchester
Department School of Electrical and Electronic Engineering
Country United Kingdom 
Sector Academic/University 
PI Contribution We have provided the University of Manchester with resources (prototype devices and instruments), knowledge (methods for testing and use of our prototype devices) and the organisation/coordination of the grant (FORTE).
Collaborator Contribution Manchester have contributed key skills and expertise in reconfigurable mixed mode circuits, reconfigurable digital PLD's and FPGAs. Manchester have agreed to fund Five PhD studentships over the period of the grant.
Impact In January Manchester, Imperial and Southampton took part in ICEIE 2020 in Barcelona and jointly ran two special sessions at the conference, which went down with such great acclaim that next year the organisers have asked to host it in London and have asked for our input.
Start Year 2018
 
Description ams AG 
Organisation AMS
Country Austria 
Sector Private 
PI Contribution Working with AMS to improve the integration of novel post-processed senor material stacks on top of CMOS. To create new sensor materials that will enable new ways to sense the environment and enable new disruptive innovations.
Collaborator Contribution AMS have agreed to provide subsidized engineering run costs and a senior engineer will follow the progress of the research plan and provide advice for disseminating and exploiting of the research outcomes.
Impact TBC
Start Year 2018
 
Title COMPUTER-IMPLEMENTED METHOD FOR CREATING ENCODED DATA 
Description A computer-implemented method for creating encoded data for use in a cognitive computing system. The method comprises the steps of receiving a plurality of hypervectors, each representing a respective semantic object; element-wise modular addition of two or more of the plurality of hypervectors, thereby binding the corresponding semantic objects; and vector concatenation of two or more of the plurality of hypervectors, thereby superposing the corresponding semantic objects. The method may be carried out by a cognitive processing unit that may be part of a cognitive computing system. 
IP Reference US2022222517 
Protection Patent / Patent application
Year Protection Granted 2022
Licensed No
Impact None yet
 
Title TUNABLE CMOS CIRCUIT, TEMPLATE MATCHING MODULE, NEURAL SPIKE RECORDING SYSTEM, AND FUZZY LOGIC GATE 
Description A tunable CMOS circuit comprising a CMOS element and a tunable load. The CMOS element is configured to receive in an analogue input signal. The tunable load is connected to the CMOS element and configured to set a switch point of the CMOS element. The CMOS element is configured to output an output current that is largest when the analogue input signal is equal to the switch point. The combination of a CMOS element with a tunable load may also provide a hardware implementation of fuzzy logic. A fuzzy logic gate comprises an input node, a CMOS logic gate including a tunable load, and an output node. The input node is configured to receive an analogue input signal. The CMOS logic gate is connected to the input node. The tunable load is provided on a current path connected to the output node. The output node is configured to output an analogue output signal. 
IP Reference US2021004669 
Protection Patent / Patent application
Year Protection Granted 2021
Licensed No
Impact None yet
 
Title NeuroPack: An Algorithm-level Python-based Simulator for Memristor-empowered Neuro-inspired Computing 
Description Emerging two terminal nanoscale memory devices, known as memristors, have over the past decade demonstrated great potential for implementing energy efficient neuro-inspired computing architectures. As a result, a wide-range of technologies have been developed that in turn are described via distinct empirical models. This diversity of technologies requires the establishment of versatile tools that can enable designers to translate memristors' attributes in novel neuro-inspired topologies. In this paper, we present NeuroPack, a modular, algorithm level Python-based simulation platform that can support studies of memristor neuro-inspired architectures for performing online learning or offline classification. The NeuroPack environment is designed with versatility being central, allowing the user to chose from a variety of neuron models, learning rules and memristors models. Its hierarchical structure, empowers NeuroPack to predict any memristor state changes and the corresponding neural network behavior across a variety of design decisions and user parameters options. The use of NeuroPack is demonstrated herein via an application example of performing handwritten digit classification with the MNIST dataset and an existing empirical model for metal-oxide memristors. 
Type Of Technology Software 
Year Produced 2021 
Open Source License? Yes  
Impact Empowers electronic designers to utilise memristors at large scales and simulate as well as emulate in silico artificial neural networks. 
URL https://arxiv.org/abs/2201.03339
 
Company Name SONET.AI LTD 
Description Sonet.ai is a company born of the ambition to embed intelligence everywhere. We drive innovation in nanotechnology, computation and artificial intelligence. Our approach empowers hardware with performance and abilities impossible to realise using only commercially available technologies. We offer unique products that can be deployed across four key computational pillars. These novel hardware solutions will equip AI systems with sensing, recognition, learning and reasoning capabilities, whilst operating at the boundaries of energy efficiency. Our vision is to ultimately combine these functionalities towards creating thinking machines. 
Year Established 2019 
Impact TBA
 
Company Name SONET.AI LTD 
Description Sonet.ai is a company born of the ambition to embed intelligence everywhere. We drive innovation in nanotechnology, computation and artificial intelligence. Our approach empowers hardware with performance and abilities impossible to realise using only commercially available technologies. We offer unique products that can be deployed across four key computational pillars. These novel hardware solutions will equip AI systems with sensing, recognition, learning and reasoning capabilities, whilst operating at the boundaries of energy efficiency. Our vision is to ultimately combine these functionalities towards creating thinking machines. 
Year Established 2019 
Impact TBA
 
Description Outreach activities in Nanotechnology 
Form Of Engagement Activity Participation in an activity, workshop or similar
Part Of Official Scheme? No
Geographic Reach National
Primary Audience Schools
Results and Impact We have delivered 3 outreach events for introducing the NanoWorld to primary school students. This was so successful that attracted the interest of the RAEng with whom we co-delivered one of the events and also Nature Nanotechnology who praised our approach by commissioning an article that describes our unique activity (Nature Nanotechnology, vol. 12, 832, 2017).
Year(s) Of Engagement Activity 2017,2018,2019
URL https://youtu.be/QoBOdwJ9ubc
 
Description STEM@Home 
Form Of Engagement Activity Participation in an activity, workshop or similar
Part Of Official Scheme? No
Geographic Reach National
Primary Audience Schools
Results and Impact Created a at home week of STEM activities for children aged between 8-11 during the national lockdown in the Summer 2020. This was very popular and the Royal Academy of Engineering then promoted it during the lockdown in January and Feb 2021.
Year(s) Of Engagement Activity 2020,2021
URL https://stemresources.raeng.org.uk/NetC.RAE/media/Resources/Engineering%20in%20the%20movies/STEM-at-...
 
Description The Future of Computing for Defence, ASTRID Framework T55 
Form Of Engagement Activity A formal working group, expert panel or dialogue
Part Of Official Scheme? No
Geographic Reach National
Primary Audience Professional Practitioners
Results and Impact FORTE technologies and public engagement activities have contributed to: a) maturing the underlying technologies and toolchain and b) bringing the opportunities of these technologies to the attention of DSTL. As a result, these became part of their targets for investigation under the "future of computation" technology landscaping exercise within the ASTRID framework. Our team is one of the two key consultants in that activity as a result of our track record in one of the major emerging technologies. Our work in emerging RRAM technologies (and in particular also work on thermodynamic computing) and our involvement in ASTRID has led to an invitation to give a talk at a KTN seminar on the future of computation . Our most recent work on thermodynamic computing was presented there.
Year(s) Of Engagement Activity 2021,2022
URL https://ktn-uk.org/events/the-future-of-computing-for-defence/