Design for high-yield manufacturing of printed circuits
Lead Research Organisation:
University of Surrey
Department Name: ATI Electronics
Abstract
Emerging printed and flexible electronics have great potential for customised consumer, medical and communication applications. In the lab they show ever-increasing performance as designer materials with specific properties are being developed. For these technologies to bridge the gap to volume production, consistency of performance and high production yield are essential, yet current progress has largely focused on individual device performance.
A type of electronic device, the source-gated transistor (SGT), was developed and patented at Surrey and operates on different principles to a conventional thin-film transistor. This device has the potential to produce uniform performance (especially drain current) despite significant parameter variation which may occur during manufacturing. SGTs can be made in a variety of technologies and in principle can be combined with conventional transistors to create high performance printed and large area electronic circuits without resorting to complicated compensation circuitry to repeatedly achieve the desired characteristics. SGTs would be ideal devices for routine operations in mass-market, low-cost printed electronics, in which their energy efficiency and uniformity of performance would outweigh the comparatively low operating speeds.
This project would be the first systematic study of both devices and low cost circuits deliberately designed to take advantage of the uniformity benefits of SGTs, with a focus on organic materials. The field of organic transistor research is particularly attractive due to the comparative ease of fabrication, rich palette of designer materials materials - both current and future, flexible substrate compatibility and low capital investment in equipment. This research has, however, now reached a plateau with the development of high-performance semiconductors, where significant improvements are likely to arise chiefly through the synthesis of improved materials. The principal hurdles for high-volume manufacturability are now the comparatively low yield and significant variations in performance, particularly over a large area. We will demonstrate the next important innovation, bringing high-volume yield to the manufacturing of low-power organic electronic technologies, by addressing these challenges.
Project partners NeuDrive (materials and devices), Silvaco (simulation), and Altro (smart living spaces) will provide essential know how in order to help achieve the project aims: to verify theoretical SGT properties by device fabrication and characterisation; to optimise the designs and assess the performance of electronic circuit blocks made with source-gated transistors; to support our findings with numerical modelling; to create design guidelines and documentation, facilitating the uptake of this new technology in both the academic and industrial environments.
CPI, the national facility for research into advanced manufacturing processes for electronics, will be subcontracted for part of the fabrication, allowing research staff to concentrate on process development, device optimisation and circuit design.
We expect the greatest value of the project to be in making possible the efficient high volume manufacturing of a wide variety of printed and flexible electronics used for wearables, sensor arrays and internet-of-things (IoT) devices, which are priorities for development in both the research community and industry. Our contribution will allow consistent performance to be obtained from printed and flexible circuits, directly increasing the market viability of a variety of cost-effective applications.
A type of electronic device, the source-gated transistor (SGT), was developed and patented at Surrey and operates on different principles to a conventional thin-film transistor. This device has the potential to produce uniform performance (especially drain current) despite significant parameter variation which may occur during manufacturing. SGTs can be made in a variety of technologies and in principle can be combined with conventional transistors to create high performance printed and large area electronic circuits without resorting to complicated compensation circuitry to repeatedly achieve the desired characteristics. SGTs would be ideal devices for routine operations in mass-market, low-cost printed electronics, in which their energy efficiency and uniformity of performance would outweigh the comparatively low operating speeds.
This project would be the first systematic study of both devices and low cost circuits deliberately designed to take advantage of the uniformity benefits of SGTs, with a focus on organic materials. The field of organic transistor research is particularly attractive due to the comparative ease of fabrication, rich palette of designer materials materials - both current and future, flexible substrate compatibility and low capital investment in equipment. This research has, however, now reached a plateau with the development of high-performance semiconductors, where significant improvements are likely to arise chiefly through the synthesis of improved materials. The principal hurdles for high-volume manufacturability are now the comparatively low yield and significant variations in performance, particularly over a large area. We will demonstrate the next important innovation, bringing high-volume yield to the manufacturing of low-power organic electronic technologies, by addressing these challenges.
Project partners NeuDrive (materials and devices), Silvaco (simulation), and Altro (smart living spaces) will provide essential know how in order to help achieve the project aims: to verify theoretical SGT properties by device fabrication and characterisation; to optimise the designs and assess the performance of electronic circuit blocks made with source-gated transistors; to support our findings with numerical modelling; to create design guidelines and documentation, facilitating the uptake of this new technology in both the academic and industrial environments.
CPI, the national facility for research into advanced manufacturing processes for electronics, will be subcontracted for part of the fabrication, allowing research staff to concentrate on process development, device optimisation and circuit design.
We expect the greatest value of the project to be in making possible the efficient high volume manufacturing of a wide variety of printed and flexible electronics used for wearables, sensor arrays and internet-of-things (IoT) devices, which are priorities for development in both the research community and industry. Our contribution will allow consistent performance to be obtained from printed and flexible circuits, directly increasing the market viability of a variety of cost-effective applications.
Planned Impact
The project studies an enabling technology for a multitude of applications. Sensor, medical and consumer uses will be brought closer to viable commercialisation by the proposed thin-film technology. Novel applications, with low power, adequate operating speed and reliable, high-yield, yet simple fabrication will bring to the market new user interfaces, monitoring devices for the elderly and "smart home" platforms. Long term, these will reduce the care burden on the health service, increase patient quality of life, and facilitate the development of new paradigms human-computer interaction, all with comparatively low capital cost.
A new class of wearable, stretchable and connected electronics with embedded sensors will be made possible by incorporating source-gated transistors in the electronic design, mostly at the interface between sensors and high performance, highly integrated circuitry, simplifying designs and reducing the time to market and design overhead. The circuit design community will have a new means of building high gain and low-power analog configurations, with bespoke behaviour, design rules and potential applications. Tutorial documentation will be produced for engineers; initial compact models and design rules will reduce the barrier to adoption of the device structure and its design approach.
Increased circuit robustness will increase viability for industries not traditionally associated with electronics to start incorporating printed electronics into their products (e.g. roll to roll manufacture of plastics, paper, wall cladding and flooring could incorporate sensors, signage and control interfaces). Companies in these sectors have already approached the PI, and this project will offer proof-of-concept data for future development and partnership.
Overseas mentoring by Prof Xiaojun Guo at Shanghai Jiao Tong University will aim to identify market opportunities for the new technology for immediate industrial uptake in emerging consumer electronic platforms such as displays, wearable sensors and smart labels, currently under advanced development in Asia.
Project partners will benefit directly by consolidating their respective leadership positions. Project insight will allow Altro to rapidly prepare ultra-low-cost, large area designs for immediate integration onto their products. NeuDrive will acquire new data on material behaviour and the scientific papers will serve to illustrate the performance advantages of their organic platform and the means of practically realising high-uniformity electronic circuits with this technology, towards fully printed organic sensors and wearables. Silvaco's thin-film transistor compact model will be refined to include a first order representation of the contact effects, based on the data from the fabrication runs; in the medium term the model will be an essential tool for SGT circuit design. Measurement results will be fed back and compared to simulation, and improvements to the TCAD routines in Atlas will be identified. Lastly, as the centre of excellence for novel electronics manufacturing in the UK, CPI may have a head start in implementing the SGT design approach, and will be in a strong position to conduct proof of principle trials for the larger design community.
Education will build on the PIs award-winning track record. The researchers involved in the project will develop multidisciplinary skills at the forefront of device and circuit design for robust flexible circuits, with great leadership potential in academic or industrial careers. Undergraduate students in Electronic Engineering will receive up to date training as state-of-the art device physics and circuit design elements are included modules taught by the PI. Emerging materials and technology will catalyse engagement activities with school children and the public, demonstrating the excitement, interdisciplinarity and bearing on society of modern electronics, and STEM in general.
A new class of wearable, stretchable and connected electronics with embedded sensors will be made possible by incorporating source-gated transistors in the electronic design, mostly at the interface between sensors and high performance, highly integrated circuitry, simplifying designs and reducing the time to market and design overhead. The circuit design community will have a new means of building high gain and low-power analog configurations, with bespoke behaviour, design rules and potential applications. Tutorial documentation will be produced for engineers; initial compact models and design rules will reduce the barrier to adoption of the device structure and its design approach.
Increased circuit robustness will increase viability for industries not traditionally associated with electronics to start incorporating printed electronics into their products (e.g. roll to roll manufacture of plastics, paper, wall cladding and flooring could incorporate sensors, signage and control interfaces). Companies in these sectors have already approached the PI, and this project will offer proof-of-concept data for future development and partnership.
Overseas mentoring by Prof Xiaojun Guo at Shanghai Jiao Tong University will aim to identify market opportunities for the new technology for immediate industrial uptake in emerging consumer electronic platforms such as displays, wearable sensors and smart labels, currently under advanced development in Asia.
Project partners will benefit directly by consolidating their respective leadership positions. Project insight will allow Altro to rapidly prepare ultra-low-cost, large area designs for immediate integration onto their products. NeuDrive will acquire new data on material behaviour and the scientific papers will serve to illustrate the performance advantages of their organic platform and the means of practically realising high-uniformity electronic circuits with this technology, towards fully printed organic sensors and wearables. Silvaco's thin-film transistor compact model will be refined to include a first order representation of the contact effects, based on the data from the fabrication runs; in the medium term the model will be an essential tool for SGT circuit design. Measurement results will be fed back and compared to simulation, and improvements to the TCAD routines in Atlas will be identified. Lastly, as the centre of excellence for novel electronics manufacturing in the UK, CPI may have a head start in implementing the SGT design approach, and will be in a strong position to conduct proof of principle trials for the larger design community.
Education will build on the PIs award-winning track record. The researchers involved in the project will develop multidisciplinary skills at the forefront of device and circuit design for robust flexible circuits, with great leadership potential in academic or industrial careers. Undergraduate students in Electronic Engineering will receive up to date training as state-of-the art device physics and circuit design elements are included modules taught by the PI. Emerging materials and technology will catalyse engagement activities with school children and the public, demonstrating the excitement, interdisciplinarity and bearing on society of modern electronics, and STEM in general.
Publications
Surekcigil Pesch I
(2022)
Multimodal transistors as ReLU activation functions in physical neural network classifiers.
in Scientific reports
Sporea RA
(2019)
Novel Tunnel-Contact-Controlled IGZO Thin-Film Transistors with High Tolerance to Geometrical Variability.
in Advanced materials (Deerfield Beach, Fla.)
Le Borgne BH
(2019)
Low-cost RC filters using materials from daily-life
Le Borgne B
(2019)
Eco-Friendly Materials for Daily-Life Inexpensive Printed Passive Devices: Towards "Do-It-Yourself" Electronics
in Electronics
Drury R
(2019)
Simulation Study of Overlap Capacitance in Source-Gated Transistors for Current-Mode Pixel Drivers
in IEEE Electron Device Letters
Bestelink E
(2021)
The Secret Ingredient for Exceptional Contact-Controlled Transistors
in Advanced Electronic Materials
Bestelink E
(2022)
Extraordinarily Weak Temperature Dependence of the Drain Current in Small-Molecule Schottky-Contact-Controlled Transistors through Active-Layer and Contact Interplay
in Advanced Electronic Materials
Bestelink E
(2020)
31-1: Invited Paper: The Multimodal Thin-Film Transistor (MMT): A Versatile Low-Power and High-Gain Device with Inherent Linear Response
in SID Symposium Digest of Technical Papers
Bestelink E
(2020)
Compact Source-Gated Transistor Analog Circuits for Ubiquitous Sensors
in IEEE Sensors Journal
Bestelink E
(2021)
Suppression of Hot-Carrier Effects Facilitated by the Multimodal Thin-Film Transistor Architecture
in Advanced Electronic Materials
Bestelink E
(2020)
Versatile Thin-Film Transistor with Independent Control of Charge Injection and Transport for Mixed Signal and Analog Computation
in Advanced Intelligent Systems
Bestelink E
(2019)
49dB depletion-load amplifiers with polysilicon source-gated transistors
Bestelink E
(2019)
Turn-off mechanisms in thin-film source-gated transistors with applications to power devices and rectification
in Applied Physics Letters
Bestelink E
(2021)
Contact Doping as a Design Strategy for Compact TFT-Based Temperature Sensing
in IEEE Transactions on Electron Devices
Bestelink E
(2020)
P-195: Late-News-Poster: Data Retention in Pixel Drivers Based on Source-Gated Transistors
in SID Symposium Digest of Technical Papers
Bestelink E
(2021)
Oxide transistors: unconventional architectures and their applications
Bestelink E
(2021)
Compact Unipolar XNOR/XOR Circuit Using Multimodal Thin-Film Transistors
in IEEE Transactions on Electron Devices
Bestelink E
(2021)
22.2: Invited Paper: Opportunities for Multimodal Thin-Film Transistors in Displays and Beyond
in SID Symposium Digest of Technical Papers
Bestelink E
(2020)
P-18: Ultra-Compact Multi-Level Digital-to-Analog Converter based on Linear Multimodal Thin-Film Transistors
in SID Symposium Digest of Technical Papers
Description | We showed that, when using source-gated transistors as emissive pixel drivers, the gate-to-source capacitance can be optimised to achieve the best performance, and the optimal value is in the region of 10um. This is contrary to conventional design rules with regular transistors, for which the best performance is obtained when this capacitance is minimised. We are fabricating organic source-gated transistors using conventional and additive manufacturing techniques. Later, we hope to prove that the performance is uniform even when geometrical variations are induced. We also showed that new barrier types can be used to induce source-gated transistor behaviour, i.e. the same beneficial effects can be achieved with structures with different composition and different underlying physics compared to conventional metal-semiconductor contacts. We showed that exceptionally high gain (almost a factor of 300 and 5-10x higher than conventional devices) can be realised in practice with voltage amplifiers of minimal complexity, namely only two source-gated transistors. We based the study on polysilicon rather than organic materials, since the gain in polysilicon is likely to be hardest to achieve due to material effects (impact ionisation), thus representing the worst case scenario. Achieving such high gain in a single amplification stage has significant benefits for the application: circuit complexity is reduced, improving manufacturability, cost and energy efficiency. |
Exploitation Route | Emerging sensors, wearables, IoT and flexible display applications can benefit from our findings, by reducing circuit complexity and increasing the robustness of the designs with a minimal number of components. This further results in low-power operation. |
Sectors | Agriculture Food and Drink Electronics Manufacturing including Industrial Biotechology Retail |
Description | The project set out design rules and processes for realising robust electronic circuits for next-generation distributed and wearable sensors. The adoption of the technology is ongoing, and the main impact is the filing of a patent for an invention concerning homeostatic temperature regulation. This is currently being pursued with a major industrial partner. We are systematically investigating the practicalities of manufacturability (materials, alignment, structure), as the main remaining challenge to industrial adoption. |
First Year Of Impact | 2022 |
Sector | Manufacturing, including Industrial Biotechology |
Impact Types | Economic |
Description | A new low-complexity paradigm for analogue computation and hardware learning |
Amount | £1,120,652 (GBP) |
Funding ID | EP/V002759/1 |
Organisation | Engineering and Physical Sciences Research Council (EPSRC) |
Sector | Public |
Country | United Kingdom |
Start | 02/2021 |
End | 10/2026 |
Description | Continuous monitoring of vascular age by pulse wave velocity using wearable ECG and PPG sensors |
Amount | £4,973,347 (GBP) |
Funding ID | ES/V00980X/1 |
Organisation | Economic and Social Research Council |
Sector | Public |
Country | United Kingdom |
Start | 11/2020 |
End | 11/2021 |
Description | Integrated flexible sensor conditioning circuits for high performance wearables |
Amount | £12,000 (GBP) |
Funding ID | IES\R2\202056 |
Organisation | The Royal Society |
Sector | Charity/Non Profit |
Country | United Kingdom |
Start | 12/2020 |
End | 12/2022 |
Description | Next-generation large area electronics through material-device-circuit co-optimization |
Amount | £12,000 (GBP) |
Funding ID | IES\R3\193072 |
Organisation | The Royal Society |
Sector | Charity/Non Profit |
Country | United Kingdom |
Start | 03/2020 |
End | 03/2022 |
Description | Free University, Bolzano |
Organisation | Free University of Bozen-Bolzano |
Country | Italy |
Sector | Academic/University |
PI Contribution | Specific expertise on high-gain transistor design |
Collaborator Contribution | Fabrication, integration and circuit design expertise. |
Impact | Ongoing |
Start Year | 2020 |
Description | Hong Kong University |
Organisation | University of Hong Kong |
Country | Hong Kong |
Sector | Academic/University |
PI Contribution | Performed advanced device simulations |
Collaborator Contribution | Fabricated and characterised electronic devices |
Impact | One paper currently under review. |
Start Year | 2020 |
Description | Kyung Hee University |
Organisation | Kyung Hee Cyber University |
Country | Korea, Republic of |
Sector | Academic/University |
PI Contribution | Simulations and electronic device design |
Collaborator Contribution | Electronic device fabrication and characterisation |
Impact | Ongoing |
Start Year | 2019 |
Title | APPARATUS FOR PRODUCING AN ELECTRICAL SIGNAL THAT IS INDICATIVE OF A TEMPERATURE |
Description | Apparatus for producing an electrical signal that is indicative of a temperature is disclosed, the apparatus comprising: a first thin-film transistor TFT comprising a first source, a first gate and a first drain, the first drain being configured to receive a reference current; and a second TFT comprising a second source, a second gate and a second drain, the first and second gates both being configured to receive the same gate voltage, wherein the first and second TFTs are configured such that a temperature dependence of the first TFT differs from a temperature dependence of the second TFT, such that an output current at the second TFT and the second drain is dependent on temperature. The temperature dependence of the output current can be controlled by selecting suitable design parameters for the first and second TFTs. A method of designing the apparatus to produce an output current with a target temperature dependence is also disclosed. |
IP Reference | WO2021038230 |
Protection | Patent application published |
Year Protection Granted | 2021 |
Licensed | No |
Impact | n/a |
Title | MULTIPLE-GATE TRANSISTOR |
Description | A multiple-gate transistor is disclosed, comprising a source, a drain spaced apart from the source, a semiconductor region disposed between the source and the drain, and an insulating region disposed over the semiconductor region. The multiple-gate transistor further comprises a current control gate for controlling a magnitude of current flowing between the source and the drain through the semiconductor region in dependence on a first electric field applied to the current control gate, the current control gate being separated from the source by the semiconductor region and the insulating region, and a switching gate for permitting current to flow between the source and the drain through the semiconductor region in dependence on a second electric field applied to the switching gate. The conduction state of the transistor (i.e. on/off) can be controlled by varying the second electric field that is applied to the switching gate, whilst the magnitude of the current through the multiple-gate transistor can be set by varying the first electric field that is applied to the current control gate. |
IP Reference | WO2020109816 |
Protection | Patent application published |
Year Protection Granted | 2020 |
Licensed | No |
Impact | Commercial opportunities for the invention are currently being explored. The authors are participating in the Lean Launch Programme in March/April 2021. Fellowship EP/V002759/1 was awarded to Sporea to continue the fundamental development of the idea. |