Automated Synthesis of High Performance Low Power Embedded Systems

Embedded computers are used in a wide range of applications from automotive control to portable media and communications devices. These are increasingly called upon to perform computationally intensive tasks which a few years ago would be considered supercomputing . Many embedded systems are portable or battery-powered and must therefore rely on a limited energy source. Designers of embedded systems are hence called upon to optimise the hardware and software so that it operates at high speed whilst consuming very little power.The number of transistors on each square millimetre of silicon doubles every 18-24 months, leading to an exponential growth in the resources available to the designers of embedded systems. However, at the same time, the relative signal transmission delays through on-chip wiring are growing alarmingly. This now means that designers cannot predict on-chip delays without actually creating the design and measuring the wire delays. Hence, the true performance and power consumption are not known until late in the design process, at which point it is too late to re-visit the design and perform high-level optimisations. In effect, the process of laying out the design of a system on silicon alters the characteristics of the system in ways that current tools are unable to predict. Manual optimisation then becomes slow, costly, and necessarily incomplete.In this project we seek to automate the design and optimisation of embedded systems. We shall do this by creating tools that are able to learn about the physical characteristics of the underlying silicon technology and use that knowledge to synthesise the structure of an embedded processor. As the processor is now a flexible entity without a pre-defined instruction set, the compiler for that processor must also be synthesised. Furthermore, the code optimisations that the compiler performs when translating from source code to the synthetic architecture, must also be synthesised.The internal structure of a processor (known as the micro-architecture) is usually hidden from the compiler. For example, the micro-architecture could implement fundamental arithmetic operations such as multiplication and division in any one of several different ways, each of which yields the same result. There are many examples like this, each one of which presents the designer with trade-offs between performance, silicon die area and energy consumption. Our research proposal also addresses these micro- architectural design alternatives. Our research will investigate ways of automating these micro-architectural trade-offs to optimise for low power consumption, high performance, and reduced die area.We therefore have three areas in which automated synthesis-must be performed: compilers; architectures; micro-architectures. However, the information on which to make automated decisions in each case will be different. At the micro-architecture level we need to know how each microarchitecture option translates into speed, energy and die area. At the architectural level we need to know how each instruction set option translates into clock cycles of execution time, and at the compiler level we need to know how each optimisation reduces the overall number of instructions executed and maximises the effectiveness of the memory system. The challenge of this research proposal is that all three areas are inter-dependent and ultimately depend on the characteristics of the silicon on which the system is based. By blurring the boundary between hardware and software, and by automating the process of adjusting that boundary, we hope to create a system that can perform design tradeoffs in seconds when currently it takes an experienced designer several days.