Energy Efficient Networks-on-Chip for Dynamically Reconfigurable Computing Platforms.
Lead Research Organisation:
University of Bristol
Department Name: Electrical and Electronic Engineering
Abstract
The purpose of this work is to investigate an on-chip network fabric that will enable future reconfigurable computing systems integrating tens or hundreds of processing tiles implementing embedded microprocessors, intellectual property cores, reconfigurable fabrics, dedicated local memories and DSP functionality. The reconfigurable NoC fabric will direct the effective communication and exchange of data among the multiple processing tiles and enable fault-tolerance and very high communication bandwidths with low-latency and low energy consumption. The processing tiles will morph their functionality and operation point based on the application demands.
People |
ORCID iD |
| Jose Nunez-Yanez (Principal Investigator) |
Publications
Nunez-Yanez J
(2012)
Cogeneration of Fast Motion Estimation Processors and Algorithms for Advanced Video Coding
in IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Nunez-Yanez J
(2011)
Multi-standard reconfigurable motion estimation processor for hybrid video codecs
in IET Computers & Digital Techniques
Beldachi A
(2014)
eXtended Torus routing algorithm for networks-on-chip: a routing algorithm for dynamically reconfigurable networks-on-chip
in IET Computers & Digital Techniques
Hosseinabady M
(2012)
Run-time stochastic task mapping on a large scale network-on-chip with dynamically reconfigurable tiles
in IET Computers & Digital Techniques
Nunez-Yanez J
(2008)
Adaptive routing strategies for fault-tolerant on-chip networks in dynamically reconfigurable systems
in IET Computers & Digital Techniques
Moctezuma J
(2015)
Biologically compatible neural networks with reconfigurable hardware
in Microprocessors and Microsystems
Hosseinabady M
(2010)
SystemC architectural transaction level modelling for large NoCs
Hosseinabady M
(2009)
Run-time resource management in fault-tolerant network on reconfigurable chips
Hosseinabady M
(2010)
Task Dispersal Measurement in Dynamic Reconfigurable NoCs
| Description | The project demonstrated flexible, adaptive routing and topology focusing on throughput, latency, energy and silicon area capable of changing the functionality in the computing nodes of the reconfigurable platform. This type of logic scaling could then be combined with voltage scaling to generate multiple functional points. ARM is further funding this area of energy efficient computing with a CASE award that looks at how nodes with different computing capabilities can be combined in a an energy efficient configuration. |
| Exploitation Route | THe technology is highly relevant to non-academic contexts such as militiary and aerospace. The technology is looking for commercial partners to continue exploitation. |
| Sectors | Digital/Communication/Information Technologies (including Software),Electronics |
| URL | http://seis.bris.ac.uk/~eejlny/reconf.htm |
| Description | The research shown that using standard FPGA devices with asynchronous technique was not viable. The lessons learnt suggested that a globally asynchronous and locally synchronous approach was preferable and continuous research in this area has generated a number of publications. The findings were also used during a Royal Society fellowship of the PI at ARM to develop power models for multi-core devices interconnected with the ARM AXI network-on-chip. |
| First Year Of Impact | 2015 |
| Sector | Digital/Communication/Information Technologies (including Software),Education,Electronics |
| Impact Types | Societal |
| Description | European Space Agency |
| Amount | £50,000 (GBP) |
| Funding ID | RQ8681 |
| Organisation | European Space Agency |
| Sector | Public |
| Country | France |
| Start | |
| Description | European Space Agency |
| Amount | £50,000 (GBP) |
| Funding ID | RQ8681 |
| Organisation | European Space Agency |
| Sector | Public |
| Country | France |
| Start | |
| Description | Royal Society of London |
| Amount | £53,000 (GBP) |
| Funding ID | RG2466 |
| Organisation | The Royal Society |
| Sector | Charity/Non Profit |
| Country | United Kingdom |
| Start | |
| Description | Royal Society of London |
| Amount | £53,000 (GBP) |
| Funding ID | RG2466 |
| Organisation | The Royal Society |
| Sector | Charity/Non Profit |
| Country | United Kingdom |
| Start | |
| Description | ARM |
| Organisation | Arm Limited |
| Country | United Kingdom |
| Sector | Private |
| PI Contribution | CASE award to develop power models for ARM big.LITTLE microprocessors |
| Collaborator Contribution | inter ships, engineering support |
| Impact | publications, PhD students. |
| Start Year | 2012 |
| Description | University of Malaga |
| Organisation | University of Malaga |
| Country | Spain |
| Sector | Academic/University |
| PI Contribution | low-power FPGA technology |
| Collaborator Contribution | Algorithms for video analysis and OpenCL implementation |
| Impact | We are writing publications on the topic that will be available soon |
| Start Year | 2015 |