Adaptive Hardware Systems with Novel Algorithmic Design and Guaranteed Resource Bounds

Lead Research Organisation: University of Edinburgh
Department Name: Sch of Engineering

Abstract

Digital processing of signals and images are frequently performed in many commercial electronic devices, including computer networks, mobile telephones and computer vision systems. A steady growth in demand for high functionality and reliability in devices such as mobile phones means that many different types of computer processors are used, from general purpose processors found in personal computers to computer chips designed to perform very specific tasks. However, at present there are no efficient design techniques that allow complex devices to be built up from a range of different computer processors. This means that current designs are often inefficient in terms of power usage and their responsiveness. Thus, a key requirement for the long-term exploitation of signal and image processing technologies lies in developing the increasingly complex processors that are required for high performance.This project addresses this need. It represents a rich inter-disciplinary collaboration between electronic engineers and computer scientists collectively aimed at overcoming fundamental challenges in high-performance computing applications. The proposed research builds on recent world-leading work in signal and image processing methods, techniques to assess the performance and complexity of computer software, and complex processor design techniques. A successful outcome to this research will allow new and efficient implementations of complex signal processing algorithms to support a diverse range of applications.

Publications

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Barrenechea M (2012) Design and Implementation of a Low-Complexity Multiuser Vector Precoder in International Journal of Embedded and Real-Time Communication Systems

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Wang Z (2009) A SDR Platform for Mobile Wi-Fi/3G UMTS System on a Dynamic Reconfigurable Architecture in 17th European Signal Processing Conference (EUSIPCO 2009)

 
Description Digital processing of signals and images are frequently performed in many commercial electronic devices, including computer networks, mobile telephones and computer vision systems. However, at present there are no efficient design techniques that allow complex devices to be built up from a range of different computer processors. This means that current designs are often inefficient in terms of power usage and their responsiveness. Thus, a key requirement for the long-term exploitation of signal and image processing technologies lies in developing the increasingly complex processors that are required for high performance.This project involved a rich inter-disciplinary collaboration between electronic engineers and computer scientists collectively aimed at overcoming fundamental challenges in high-performance computing applications. The work was structured in three major work packages. The first work package developed new implementations of algorithms developed using a new computer language called HUME onto field programmable gate array (FPGA) devices. The second work package developed new efficient processor designs for algorithm implementation on FPGAs and new detection algorithms for wireless communications. The third work package studied new serial and parallel implementation techniques for Lidar systems and new wireless algorithm designs for wireless communications.More specificially, the research work at Edinburgh developed new efficient detection algorithms for multiple input-multiple output (MIMO) wireless systems, which use multiple antennas at both transmitter and receiver. These algorithms are more energy efficient than the state of the art fixed sphere decoder (FSD) algorithms. A new approach to soft-decoding in MIMO systems, called the parallel candidate scheme, was developed to reduce implementation delay compared to existing algorithms. Finally, the performance of transmitter precoding schemes for orthogonal frequency division multiplexing (OFDM) signals was studied and shown to provide a low complexity alternative to complex receiver processing algorithms such as the FSD approach.
Exploitation Route Our work in the second work package has developed new mathematical algorithms for detecting wireless communications signals in the presence of multiple antennas. The methods we have devised will be of use to other researchers and developers working on practical signal processing algorithms for this scenario.
Sectors Digital/Communication/Information Technologies (including Software)

URL http://www.see.ed.ac.uk/~idcomislay/
 
Description The principal investigator organised a special session on " Efficient Implementation of Complex Algorithms" at the Eurasip EUSIPCO conference held in Glasgow in August 2009. The idea of this session was to present the initial research findings from the project to the research community and to discuss efficient hardware implementation issues with the audience. In September 2010, the principal investigator was invited by Dr Gunther Auer of NTT Docomo Research Labs in Germany to give a presentation on his work at the EUWIT Conference, held in Paris in Sept 2010. This presentation was given as part of a special session on future wireless technologies. Beneficiaries: Academic researchers in the field, especially those who attended the meetings described.
First Year Of Impact 2009
Sector Digital/Communication/Information Technologies (including Software)
Impact Types Societal

 
Description Cognovo
Amount £6,000 (GBP)
Funding ID Cognovo 
Organisation CogNovo 
Sector Academic/University
Country United Kingdom
Start 01/2010 
End 12/2010
 
Description EPSRC
Amount £1,041,266 (GBP)
Funding ID EP/J015180/1 
Organisation Engineering and Physical Sciences Research Council (EPSRC) 
Sector Public
Country United Kingdom
Start 06/2012 
End 05/2016
 
Description EPSRC/DSTL Programme Grant
Amount £3,837,581 (GBP)
Funding ID P/K014277/1 
Organisation Engineering and Physical Sciences Research Council (EPSRC) 
Sector Public
Country United Kingdom
Start 04/2013 
End 03/2018