Variation-Adaptive Design in FPGAs

This proposal is concerned with design techniques to compensate for parametric variations in deep-submicron configurable digital circuits. The growth of the microelectronics industry over the last four decades has been based on reducing the size of transistors to make integrated circuits smaller, faster and less expensive. The benefits obtained by transistor scaling are now diminishing as it becomes increasingly difficult to control the spread of parameters within a single chip.The research in this proposal will investigate new variation-aware design techniques in deep-submicron programmable logic devices. This is well-aligned with the recently developed Microelectronics Grand Challenges'' roadmap, particularly GC3---Moore for Less''. The premise for the research is that a single design can be implemented in more than one way in a given programmable logic device. In the presence of variations, distinct implementations will exhibit different performances, although they are functionally identical.The intention is to discover and develop strategies which exploit this feature in existing programmable logic devices. Furthermore, architectural modifications to such devices will be proposed to increase the obtainable benefit. These goals will be achieved from a thorough analysis of the nature of parametric variability from empirical studies, followed by the rigorous use of probabilistic modelling and optimisation theory.