PAnDA: Programmable Analogue and Digital Array

Moore's law states that, since their invention in 1947, every two years the number of transistors on an integrated circuit doubles. This is due to the shrinking of devices through advances in technology. However, as these devices are approaching the atomistic level, intrinsic variations are becoming more abundant, leading to a lower production yield and higher failure rates. In order to accommodate the increased variability of individual device characteristics there is a need for novel device architectures and circuit design methodologies. For example, Intel were forced to make the biggest change in transistor technology since the 1960s in order to reach the 45nm CMOS technology node. These predictions and issues were originally focussed on large-scale integration, mainly connected with microprocessor design. However, in the last 10 years the rise of Field Programmable devices (e.g. Field Programmable Gate Arrays - FPGA) both in terms of technology advances and application domains has meant that these issues are now relevant to these devices as well. Hence, the proposal focuses upon one of the current greatest challenges in electronic design: taking physical effects of intrinsic variability into account when the shrinking of device sizes approaches atomistic levels, in order to achieve functional circuit designs. Both process and substrate variations impose major challenges on the reliable fabrication of such small devices. These variations fall into two categories; deterministic variability, which can be accurately modelled and accounted for using specific design techniques, and stochastic variability, which can only be modelled statistically and is harder to overcome. The proposal will develop a reconfigurable design platform that can be manipulated at the device and digital abstraction levels in order to further understand and tackle the effects of stochastic variability in hardware upon next generation designs.The research proposal comprises four threads that build upon each other:- Design of a simulation model for a variability tolerant architecture, - Hardware realisation of this model,- Development of a comprehensive software framework, which will be able to interface the simulation model as well as the chip,- Development of bio-inspired approaches to tackle variability tolerant design. At its conclusion the project will have developed an understanding of how stochastic variability will affect circuit design in the future and will propose novel design methodologies to overcome stochastic variability. A novel, variability tolerant architecture will have been developed and realised as a simulation model and as a prototype in hardware. Both are vital steps towards next generation FPGA architectures.

The PAnDA design platform will provide a unique design and research platform using a modern semiconductor technology. It will have the potential to optimise existing, or create novel electronic designs and standard cell libraries with respect to variability tolerance and power consumption without actually having to produce them. For the first time, an FPGA architecture will be available which also provides access to the underlying analogue layer in order to manipulate circuit characteristics. This kind of low-level post-place-and-route access to configured designs provides a whole new entry point for design optimisation strategies/algorithms/tools. Hence there are a wide range of potential beneficiaries: FPGA vendors, such as Xilinx, Altera, and Actel, as well as the FPGA design and application industry would be able to extend their design synthesisers with the option to optimise for stochastic variability, which would potentially accelerate the feasibility of sub-40nm technologies for FPGAs and facilitate high-level design with those FPGAs for a wide range of applications, including digital signal processing, aerospace & defence systems, ASIC prototyping, image/data processing and computer vision. Tool chain providers, such as Cadence, Synopsys and Mentor Graphics would be able to include, for example, the statistical analysis modules for stochastic variability and design optimisation algorithms, which will be essential tools for successful electronic design at sub-40nm technology nodes, which would significantly benefit the semiconductor design industry and standard cell designers by providing them with more accurate and reliable simulation results. The semiconductor fabrication industry, such as IBM, Intel and Samsung will potentially also benefit from the outcome of this research into stochastic variability. PAnDA as an actual hardware design platform offers a unique possibility to the semiconductor design industry, such as ARM, and Toshiba who could use it as a rapid prototyping platform for their IP cores at a smaller technology node, which would shorten time-to-market. In the same way designers of standard cell libraries and device modellers, such as semiconductor fabs, and GSS would benefit from optimisation algorithms and accelerated testing via a hardware platform when designing variability enhanced device models and standard cell libraries. Furthermore, ASIC designers could save significant amounts of time, particularly in the early stages of the design process, using PAnDA as a hardware-in-the-loop stochastic variability analysis tool to improve design productivity. All previous impact factors potentially lead to the benefit of the FPGA industry as a whole, as they might contribute to an early adoption and feasibility of sub-40nm technologies.