High permittivity dielectrics on Ge for end of Roadmap application

The semiconductor industry is now driven largely by applications pull for mass market consumer goods and it is essential that circuit performance is continually improved if the insatiable demand for such products is to be satisfied. The continuing miniaturisation of transistors within CMOS circuits or 'chips' results in degradation of transport properties in the Si-based MOS transistor channels resulting in reduced drive current and hence circuit speed. It is also increasingly difficult to engineer transistors wherein the ultra-short channel (10s of nanometre) is controlled exclusively by the gate electrode; so-called 'short channel effects'. To control this latter effect, increasingly thin gate dielectric is required (circa 2nm) but this leads to excessive leakage curent through the gate through the quantum mechanical tunnelling effect. This gate leakage compromises the operation of the transistor and most importantly, gives rise to very considerable power consumption which reduces battery lifetime in portable products, and also contributes to severe heating of the chip. The use of a dielectric with a higher permittivity (k) allows for a thicker gate oxide with much reduced leakage, whilst maintaining the drive current of the transistor.Germanium semiconductor was used for the very first transistors and possesses excellent transport properties, far superior to those of Si. The successful integration of hafnia based dielectrics for the MOS gate stack, first by Intel, closely followed by other major companies, has been instrumental in installing a new radicalism into the industry. Thus there is now considerable interest incorporating a Ge pMOST and either Ge or a III/V material for the nMOST within CMOS gates. The disadvantage of the lack of a good native oxide for the case of Ge is now mitigated by the availability and proven nature of deposited dielectrics. The combination of a high mobility channel made in Ge, and a reliable hi-k gate dielectric, is highly desirable. The central aim of this project then is to advance the knowledge and underlying science of Ge MOSFETs, crucially in the area of the gate stack. In particular, rare-earth dielectrics on Ge offer the possibility of a 'magic bullet' solution: a fully scaleable gate stack on a high mobility channel, to the end of the CMOS road map dictated by 'Moore's Law.' Hafnia-based gate stacks are at a more advanced stage in the field but require an interfacial layer which calls for further study into the stability of the native oxide (GeO2) and a technological solution for surface passivation. The 'k' can be increased by doping of the hafnia. There is a pressing need to understand the physics underlying the turn-on or threshold voltage of Ge transistors, which is affected by parasitic 'acceptor-like' energy states near the valence band edge and hence find an engineering solution. New measurement techniques need to be developed to assess phenomena peculiar to Ge devices. Furthermore, the reliability has hardly been looked at for Ge oxide stacks. There are certainly a radically different set of issues compared to Si which will have, in turn, an impact on the suitable materials in the gate stack. Interface states near the conduction band edge are thought to be responsible for the low electron mobility which is proving a 'killer' for the nMOST. These technological challenges will be addressed in this project, by a team who have individually and collaboratively, had active participation in dielectrics research over a period of decades. The team cover the subject from atomistic level theory and modelling, through screening of novel materials and chemical precursors, growth and deposition, fabrication, physical and electronic characterisation; to reliability testing. The group members have very strong links into industry and research institutions along this chain of expertise.

The project team envisages the development of new manufacturing process steps for CMOS technologies beyond the 22nm node, with proven reliability. The application of atomic layer deposition (ALD) for the manufacture of a high-k dielectrics for germanium-based semiconductor devices, constitutes a potential, significant advance in this field. The innovations arising from this project are essentially three-fold. Firstly, ALD technology is being extensively developed for the microelectronics industry and for flat panel display products. This project will exploit the ability of ALD for control of the germanium - dielectric interface and for the subsequent high-k deposition. It is envisaged that ultimately the ALD high-k process will deliver a CMOS process suitable for the next generations of processor devices. SAFC Hitech will receive direct benefit from the outcomes of the research as will Umicore who supply Ge wafers to the industry. Secondly, the project has the potential to develop new precursor materials, specifically tailored for germanium-based electronic devices. The drivers here are cost reduction; precursor shelf life and ease of handling; useful yield; and recycling of waste. The precursors will also have the potential for 'spill-over' applications from the Electronics Industry to others which requires advances in both conductive and dielectric thin film materials. These precursors will have applications in other market sectors across the broader field of thin film nanotechnolgy. The specific applications where hi-permittivity dielectrics can make a major impact are as follows: photovoltaics, catalysts, plastic electronics, high precision passive components for system-on-chip with applications rf, low power electronics and medical electronics; high value 'super capacitors' for storage in energy harvesting systems (no battery electronics) and others. Thirdly, the team can also foresee a major contribution and impact into the underlying reliability science which will provide the ultimate benchmark for these new materials. The results will therefore be demonstrably 'technologically relevant'. IMEC are a world leading Research Institute providing research and development ahead of industrial needs by 3 to 10 years, in nanoelectronics, nanotechnology, design methods and technologies for ICT systems. They provide a gateway into major international semiconductor companies, providing the possibility to greatly enhance the technological and scientific impact of the research. Finally, the multi-disciplinary nature of the project will provide a superb training environment for young scientists employed on the project, extending from fundamental modelling and growth science through to devices. The research will receive wide dissemination through a broad range of conferences and workshops which have high levels of industrial participation.