Highly-parallel algorithms and architectures for high-throughput wireless receivers

During the past two decades, reliable wireless communication at near-theoretical-limit transmission throughputs has been facilitated by receivers that operate on the basis of the Bahl-Cocke-Jelinek-Raviv (BCJR) algorithm. Most famously, this algorithm is employed for turbo error correction in the Long Term Evolution (LTE) standard for cellular telephony, as well as in its previous-generation predecessors. Looking forward, turbo error correction promises transmission throughputs in excess of 1 Gbit/s, which is the goal specified in the IMT-Advanced requirements for next-generation cellular telephony standards. Throughputs of this order have only very recently been achieved by State-Of-the-Art (SOA) LTE turbo decoder implementations. However, this has been achieved by exploiting every possible opportunity to increase the parallelism of the BCJR algorithm at an architectural level, implying that the SOA approach has reached its fundamental limit. This limit may be attributed to the data dependencies of the BCJR algorithm, resulting in an inherently serial nature that cannot be readily mapped to processing architectures having a high degree of parallelism.

Against this background, we propose to redesign turbo decoder implementations at an algorithmic level, rather than at the architectural level of the SOA approach. More specifically, we have recently been successful in devising an alternative to the BCJR algorithm, which has the same error correction capability, but does not have any data dependencies. Owing to this, our algorithm can be mapped to highly-parallel many-core processing architectures, facilitating an LTE turbo decoder processing throughput that is more than an order of magnitude higher than the SOA, satisfying future demands for gigabit throughputs. We will achieve this for the first time by developing a custom Field Programmable Gate Array (FPGA) architecture, comprising hundreds of processing cores that are interconnected using a reconfigurable Benes network. Furthermore, we will develop custom Network-on-Chip (NoC) architectures that facilitate different trade-offs between chip area, energy-efficiency, reconfigurability, processing throughput and latency. In parallel to developing these high-performance custom implementation architectures, we will apply our novel algorithm to both existing Graphics Processing Unit (GPU) and NoC architectures. This will grant us a rapid pace, allowing us to apply our novel algorithm to not only error correction, but to all aspects of receiver operation, including demodulation, equalisation, source decoding, channel estimation and synchronisation. Drawing upon our high-throughput algorithms and highly-parallel processing architectures, we will develop techniques for holistically optimising the algorithmic and implementational parameters of both the transmitter and receiver. This will facilitate practical high-performance schemes, which can pave the way for future generations of wireless communication.

This research addresses key EPSRC priorities in the Information and Communication Technologies theme (http://www.epsrc.ac.uk/ourportfolio/themes/ict), including 'Many-core architectures and concurrency in distributed and embedded systems' and 'Towards an intelligent information infrastructure'. The 'Working together' priority is also addressed, since this cross-disciplinary research will develop new knowledge that spans the gap between high-performance communication theory and high-performance hardware design. This research will offer new insights into the design of many-core architectures, which the hardware design community will be able to apply in the design of general purpose architectures. Furthermore, the communication theory community will be able to apply our algorithms across even wider aspects of receiver operation.

This research will enable significant economic and societal benefits, since we will closely engage with our broad range of industrial partners, helping them to develop wireless receivers with significantly improved processing throughputs. This will remove the bottleneck imposed upon the transmission throughput of wireless communication systems employing SOA components. As a broader benefit, future wireless communication systems may also employ the results of our research for SOA source decoding, demodulation, equalisation, channel estimation and synchronisation. This will facilitate the near theoretical limit exploitation of limited bandwidth, hence resulting in significant societal benefits, allowing more wireless communication services to be offered to the public. Furthermore, the proposed highly-parallel turbo decoders are compatible with the Long Term Evolution (LTE) cellular telephony standard, as well as with its predecessors and successors. Owing to this, our turbo decoders can be employed in cellular handsets and base stations throughout the world, within ten years. The UK is already a world leader in general purpose parallel processing and the proposed research will grant the UK a significant head-start in parallel processing for wireless communications, creating significant economic benefits.

The proposed research will be of significant benefit to our three industrial partners, as stated in the corresponding Letters of Support. The design of highly-parallel algorithms and architectures for high-throughput wireless receivers is of significant interest to Altera. In particular, Altera wish to engage with this research, so that they can demonstrate the suitability of their highly-parallel processing platforms to these new areas. Furthermore, this research will develop some soft Intellectual Property (IP), which Altera will market commercially. Similarly, ARM already has a significant involvement with our team through the ARM-ECS Research Centre (http://www.arm.ecs.soton.ac.uk), with a particular interest in the proposed co-design of algorithms and architectures for high-throughput wireless receivers. More specifically, ARM is already leading the world in general purpose processing architectures and they are eager to reproduce this success in wireless communication. Finally, as one of the world's leading communications services companies, BT has a significant interest in the proposed research, which will enable high-throughput wireless services. In particular, BT is an active participant in communications standardisation, offering a route for the proposed research to influence future standards.

Throughout his PhD, the named Research Assistant (RA) Shaoshi Yang has gained significant expertise in designing communication algorithms having both a high performance and a low complexity, as shown in the attached CV. This combination is highly sought after in both UK industry and academia, since it facilitates holistic design, which can yield significant benefits like those described in this proposal. The experience that the named RA and the second RA will gain from their involvement in this proposal will significantly further develop their expertise. In addition to developing the expertise of the Principal Investigator (PI), undertaking this role will further develop his project leadership skills. The experience that the PI gains from managing this work and his team will enable him to undertake even more ambitious projects in the future, having greater scope and impact. Furthermore, the liaison with academia and industry detailed in this proposal will provide valuable networking opportunities for the PI. In the future, this will provide him with further opportunities to collaborate and undertake work with broader scope and impact. Furthermore, the PhD student funded by Altera will follow in the RAs' footsteps, gaining valuable expertise in both communication algorithms and hardware design.