TESiC-SuperJ - Trench Epitaxy for SiC Superjunctions: technology enabling low loss HVDC power electronics.

Lead Research Organisation: University of Warwick
Department Name: Sch of Engineering

Abstract

In 2019 48.5% of the 32 GW daily average energy demand in the UK was carbon-free - contributed by wind farms, solar and nuclear energy, alongside energy imported by subsea interconnectors and biomass. This trend supports the "net zero" commitment signed by the government in 2019. However, significant technologies still need to be developed to enable this goal. One key such technology is high voltage direct current (HVDC) grid level transmission which will enable the "supergrid". This is a network of long distance power transmission lines across and between countries and those aforementioned energy production facilities, particularly in remote locations such as offshore wind farms. Increasing the efficiency and power rating of each grid interconnection (as well as reducing their volume and weight) it would mean more widespread implementation and hence better energy security, lower carbon footprint and better energy economy for the UK.

Within most interconnectors, 50% of the volume is the power electronics devices, traditionally made from Silicon technology. Silicon Carbide (SiC) has clear advantages over current Silicon technology such as high temperature and higher frequency operation, with lower resultant system weight and volume. Recently, commercially available SiC power devices have recently entered the market with force, predicted to be worth $2bn by 2024, with rapid growth in this technology is being actively driven by a number of early adopters in the automotive sector, e.g. Tesla. However for high voltage (>1.7 kV) power transmission, bipolar Silicon devices (IGBTs, GTOs) are more efficient - so the technology must presently be chosen relative to application. To remove this restriction, SiC power devices of all types can be additionally bolstered by SuperJunction (SJ) technology, improving the efficiencies of the material and fully ready to challenge Si technology.

This proposal intends on developing new 6.5 kV SiC SJ materials and devices technology for the goal of increased power transmission. Current research in SiC SJ devices consists only of a handful of reports on single devices, whilst encouraging, the technology is still in its infancy. The UK has an opportunity to develop the technology from the ground up and become a serious international name. The major challenge being that SiC processing methods fall short of being able to mass-produce the superjunction material, with one method being expensive and complicated, another requiring very tight precision of parameters and the last compromising on current rating.

Specifically here we propose to develop Trench Epitaxy (TE), which deposits crystalline materials in very high aspect ratio micro trenches. The deposition method is chemical vapour deposition (CVD), which is accepted as the industry gold standard of fast throughput, high quality materials production and so must be the method of choice when developing this technology. The challenges in developing TE lie in the transport of the gases to the bottom of the trenches to a) etch the material, b) condition it ready for deposition and c) fully refilling the trenches with modified material and d) ensuring the surface is returned to its previous state. The more complex challenges lie in the non-mutually exclusive chemical nature of the work, where a change in one parameter may change many more.

Warwick currently houses the only industrial SiC CVD in the UK, has a dedicated SiC device fabrication cleanroom and many analytical tools so is the ideal place for the UK to enter this field with the view to contributing to the technology at the point of entry. The University of Warwick is a key member of EPSRC Centre for Power Electronics and is part of the £17M APC-12 ESCAPE (End-to-end Supply Chain development for Automotive Power Electronics) project which is developing a UK centred SiC production line, led by McLaren, so pathways exist of fully implementing TE SiC SJ technology after development.

Publications

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Description A Plasma Polish Dry Etch process to prepare 4H-SiC substrates for device fabrication. 
Organisation Oxford Instruments Plasma Technology
Country United Kingdom 
Sector Private 
PI Contribution Oxford Instruments developed the PPDE process, Warwick provided epitaxy and materials anlaysis.
Collaborator Contribution Silicon Carbide (4H-SiC) is an ideal material for high-voltage (>1.2kV), harsh environment and temperature operation devices because of its high critical electric field, excellent thermal conductivity, and material maturity [1-2]. However, its substrate price is still a large component of the overall device production and hinders technological implementation, where the process includes boule growth, sawing, grinding and polishing [3]. A flat (< 10µm bow), low roughness (< 1nm) and damage-free substrate surface is crucial for subsequent epitaxy and device fabrication - normally achieved by Chemical and Mechanical Polishing (CMP). Prior to CMP, subsurface damage can be created by the lapping and grinding processes and if this subsurface damage is not removed then defects can propagate through the following epilayer and reduce device yield [4]. A disadvantage of using CMP is that some subsurface damage effects can remain afterwards and can impact the subsequent SiC epi-deposition by mean of propagation of defects from the substrate and new formation of defects that are detrimental for some devices such as diodes and MOSFETs. [5] In this study, a new method to replace CMP involving a Plasma Polish Dry Etch (PPDE) process is reported. PPDE can offer many advantages over CMP, including lower production costs, reduction of wafer breakage, reduction of wet chemical usage, cross wafer uniformity, reproducibility and even application post-epitaxy. [6-7] The PPDE process has been carried out by ICP/RIE in an Oxford Instruments PlasmaPro100 etcher on the Si face of 150 mm 4H-SiC 325 µm 4° offcut substrates without CMP
Impact Talk at conference ICSCRM 2022: A Plasma Polish Dry Etch process to prepare 4H-SiC substrates for device fabrication.
Start Year 2021