High Performance Computing - ASiMoV

Bristol's ASiMoV work package contains 5 suggested avenues of research, of which 3 are
areas that I am both highly enthusiastic about and are areas that I believe I can add
significant value to.
The first of these avenues looks at anticipated next generation processor features, and how
these can be exploited for HPC. An example of these is ARM's Scalable Vector Extension
(SVE). ARM's previous 128-bit NEON architecture has already been shown to
1
have comparable performance with many Intel systems [7], and therefore the large 2048 bit
registers of SVE - and the newly announced SVE2 - prove exciting contenders for Exascale
systems [8, 4].
Aside from future modifications to traditional processors, the popularity of neural networks
has lead to the emergence of specialized AI hardware, including Intel's Nervana, IBM's
TrueNorth and Google's TPU. A notable local startup, Graphcore, has also secured $200
million to develop their AI chip, the Intelligence Processing Unit (IPU) [2]. It is claimed that
this chip can outperform conventional CPUs and GPUs by 1-2 orders of magnitude when
training neural networks [3]. Certainly, an interesting aspect of a PhD at Bristol will be
identifying the strengths of these chips in relation to the ASiMoV project, and if possible,
exploiting these for 'general purpose' computing in HPC. Due to the large amount of
industrial resources being given to developing these AI chips, and the limited research in
the area, now is an critical time to identify how HPC can capitalize on them.
With the evolution of these specialized accelerator technologies and the prominence of
CPUs and GPUs in current HPC systems, there is more motivation then ever before to
establish techniques for achieving performance portability. The Bristol HPC research group
has already been working on achieving this for several of the computational dwarfs [1, 6, 9,
5], and will look to extend this to the ASiMoV solvers being developed by the Universities of
Oxford and Cambridge. Writing performance code on new systems requires both technical
knowledge and considerable financial resource, thus it is vital that more work is done to
attain performance portability across systems.