DSP Architecture: efficiency of accelerators in high throughput computations

The main idea of this research is to develop new Digital Signal Processor (DSP)

architectures for the efficient control of embedded accelerators.

It can be difficult to define what embedded systems are, but a characteristic

feature is that they are not general purpose systems, but are systems which are

designed to perform a specific set of tasks.

Previous work in this area has not addressed the challenges of real-time many

threaded architectures, including the key task of coordinating large number of

streaming accelerators.

Also, simultaneous multithreading technology has so far not been used in

embedded systems, mainly because embedded systems tend to require real-time

determinism.



This proposal aims to answer the following questions:

- Can computations be performed more efficiently in software defined radio

applications?

- Can task scheduling of multithreaded systems be made more deterministic for

real-time control applications?



The fundamental challenges to be addressed by this proposed research are:

- How to optimize DSP architectures to support real-time control of embedded

accelerators, with reference to applications such as

Software Defined Radio (SDR);

- In high-throughput computation, involving real-time DSP architectures, how can

frequently used DSP tasks be offloaded to accelerators in the most efficient

way;

- Can the DSP processor be rearchitected to support other types of

high-throughput numerical computations such as deep learning;

- Would expanding the instruction set of a generic processor with DSP/SDR

specific instructions give similar performance gains;

- The implementation and control of accelerator blocks within a potentially

multithreaded design and achieving more determinism within multithreaded

embedded processors



Fundamentally, the unifying question is: can digital signal processors be made

faster, more efficient and be utilized in more varied applications?