NBTI and leakage aware sleep transistor design for reliable and energy efficient power gating (2015)

First Author: Rossi D
Attributed to:  Resilient and Testable Energy-Efficient Digital Hardware funded by EPSRC

Abstract

No abstract provided

Bibliographic Information

Digital Object Identifier: http://dx.doi.org/10.1109/ets.2015.7138752

Publication URI: http://dx.doi.org/10.1109/ets.2015.7138752

Type: Conference/Paper/Proceeding/Abstract