Statistical analysis of stencil technology for wafer-level bumping (2014)

First Author: W. Kay R
Attributed to:  An Innovative Electronics Manufacturing Research Centre funded by EPSRC

Abstract

No abstract provided

Bibliographic Information

Digital Object Identifier: http://dx.doi.org/10.1108/ssmt-07-2013-0017

Publication URI: http://dx.doi.org/10.1108/ssmt-07-2013-0017

Type: Journal Article/Review

Parent Publication: Soldering & Surface Mount Technology

Issue: 2

ISSN: 0954-0911