Design of a DCO based on worst-case delay of a self-timed counter and a digitally controllable delay path (2016)

First Author: Benafa O
Attributed to:  Dream Fellowship: Energy-Modulated Computing funded by EPSRC

Abstract

No abstract provided

Bibliographic Information

Digital Object Identifier: http://dx.doi.org/10.1109/NEWCAS.2016.7604821

Publication URI: http://dx.doi.org/10.1109/NEWCAS.2016.7604821

Type: Conference/Paper/Proceeding/Abstract