Tile size selection for optimized memory reuse in high-level synthesis (2017)

First Author: Liu J
Attributed to:  PRiME: Power-efficient, Reliable, Many-core Embedded systems funded by EPSRC

Abstract

No abstract provided

Bibliographic Information

Digital Object Identifier: http://dx.doi.org/10.23919/fpl.2017.8056810

Publication URI: http://dx.doi.org/10.23919/fpl.2017.8056810

Type: Conference/Paper/Proceeding/Abstract