Design Flow for Hybrid CMOS/Memristor Systems-Part II: Circuit Schematics and Layout (2021)

First Author: Maheshwari S
Attributed to:  Functional Oxide Reconfigurable Technologies (FORTE): A Programme Grant funded by EPSRC

Abstract

No abstract provided

Bibliographic Information

Digital Object Identifier: http://dx.doi.org/10.1109/tcsi.2021.3122381

Publication URI: http://dx.doi.org/10.1109/tcsi.2021.3122381

Type: Journal Article/Review

Parent Publication: IEEE Transactions on Circuits and Systems I: Regular Papers

Issue: 12