Tagged Repair Techniques for Defect Tolerance in Hybrid Nano/CMOS Architecture (2011)

First Author: Srivastava S

Attributed to: Electronics Design funded by EPSRC

Abstract

No abstract provided

Bibliographic Information

Digital Object Identifier: http://dx.doi.org/10.1109/tnano.2010.2045393

Publication URI: http://dx.doi.org/10.1109/tnano.2010.2045393

Type: Journal Article/Review

Parent Publication: IEEE Transactions on Nanotechnology

Issue: 3