Development of cryo-CMOS to enable the next generation of scalable quantum computers

Lead Participant: SURECORE LIMITED

Abstract

Modern life is unthinkable without computers. An ever-increasing amount of energy is required for computing, impacting the global drive to a low-carbon economy, and Moore's law is slowing as the circuit dimensions approach physical limits. Quantum computers can create a computational space much larger than their classical counterparts. They will shape computing, science and commercial standards by solving numerical problems that are currently out of reach in fields including chemistry, material science, logistics, artificial intelligence, machine learning and cryptography.

The race is on to build the world's first practical quantum computers, which requires scaling from arrays of a few dozen qubits, to thousands, to millions of qubits. To achieve this, we need to create integrated systems of qubit arrays and control electronics. In most implementations, the qubits require cryogenic cooling, typically to a fraction of a degree above absolute zero. Yet conventional CMOS electronics is designed to operate at room temperature, and if these chips are cooled to cryogenic temperatures, the operating characteristics of the transistors change markedly, and they no longer work as intended.

This problem is well recognised in the industry. Major players such as Google, Microsoft and Intel have all invested in progressing towards building specialised "cryo-CMOS" control electronics that can operate in the very cold environment that the qubits require.

Most quantum computing companies, however, don't have the resources to develop silicon CMOS processes for cryogenic temperatures. Instead, they rely on semiconductor fabrication via foundries (e.g., TSMC, Globalfoundries), looking to various silicon IP companies to provide technology to enable them to exploit the foundries' manufacturing capability. This model has worked well for development of chips for room temperature operation, however it requires significant updating to create new designs that can work at ultra-cold temperatures.

This project brings together world-leading expertise in CMOS design and quantum computing. We will create updated process design kits (PDKs) for cryogenic temperatures and an ecosystem of silicon IP products to enable chip designers to exploit foundries using the established fabless model. Thus the project will enable quantum computing companies to scale their hardware systems to create a new generation of more powerful quantum computers.

Lead Participant

Project Cost

Grant Offer

SURECORE LIMITED £2,282,588 £ 1,597,812
 

Participant

UNIVERSITY OF GLASGOW
SYNOPSYS (NORTHERN EUROPE) LIMITED £95,630 £ 47,815
SEEQC UK LIMITED £1,037,777 £ 726,444
SEMIWISE LIMITED £744,410 £ 521,087
UNIVERSAL QUANTUM LTD £1,075,271 £ 752,690
OXFORD INSTRUMENTS PLASMA TECHNOLOGY LIMITED
UNIVERSITY OF GLASGOW £1,162,790 £ 1,162,790
OXFORD INSTRUMENTS NANOTECHNOLOGY TOOLS LIMITED £76,306 £ 38,153
INNOVATE UK

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