Nanometre Strain Evaluation for Future and Emerging Technologies

Strain will play a vital role in future and emerging electronic technologies. By 2016 silicon-based integrated circuits in production will feature gate lengths below 10 nm. Many new materials and processing modules will be necessary to maintain the doubling in performance seen every 18-24 months over the last 40 years, known as Moore's Law. Strain is crucial because of its impact on both electrical and material properties. Using controlled amounts of strain increases electron and hole mobilities in silicon, while too much strain causes material defects. The aim of this project is to engineer strain in electronic devices in order to boost their performance. The project will make a major contribution to the paucity of techniques available for accurate measurements of strain at small geometries by developing new methods for sensitive profiling and analysis of strain on a sub-nm scale. These techniques will be used to assess the impact of material growth and device fabrication on the strain state of new materials as-grown and their subsequent robustness to high thermal budget processing. The final strain state of future nanoelectronics devices will be engineered through a combination of local and global strain contributions. Accurate correlations between electrical performance with strain measurements in material and devices will be developed to enable the necessary feedback between materials, processing and devices to achieve best possible solutions.