Optimising Hardware Acceleration for Financial Computation
Lead Research Organisation:
Imperial College London
Department Name: Computing
Abstract
This proposal describes a three-year research project exploring novel methods and tools for hardware acceleration of financial computation in general, and for Monte Carlo simulation of financial models in particular. Our aim is to exploit the latest software and hardware technologies, particularly those based on advanced reconfigurable hardware such as FPGAs (Field-Programmable Gate Arrays), and to demonstrate the effectiveness of these technologies by applying them to overcome bottlenecks in current and future large-scale financial computation. The technical innovations of this project includes: (1) parameterisation, characterisation and efficient implementation of novel hardware architectures for financial computations; (2) exploitation of the latest software and hardware technologies, such as source-level transformation and advanced reconfigurable gate arrays; (3) techniques for reducing heat dissipation by extensive pipelining, (4) elements for an evolutionary approach to support hardware acceleration for financial analysis, such as adoption of commercial FPGA platforms, facilities to make the technology accessible to finance experts, comparison of standard fixed-point and floating point arithmetic, incremental compilation, and interface to grid technology; (5) elements for a disruptive approach to support hardware acceleration, such as run-time optimisation, coarse-grained devices, non-standard arithmetic, new application opportunities such as real-time risk analysis, and new platform and chip architectures; (6) static and dynamic customisations for adapting architectures to changes in environmental conditions to maintain effective operation, while meeting various constraints such as performance and power consumption; (7) prototype development frameworks for designing and deploying novel architectures supporting financial computations, by combining and specialising our libraries and tools; (8) large-scale applications, based on our experience in financial simulation, to drive the development of architectures and tools for novel computations.
Publications
Chun Hok Ho
(2009)
Floating-Point FPGA: Architecture and Modeling
in IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Jin Q
(2009)
Exploring Reconfigurable Architectures for Tree-Based Option Pricing Models
in ACM Transactions on Reconfigurable Technology and Systems
Morris G
(2009)
FPGA Accelerated Low-Latency Market Data Feed Processing
Thomas D
(2008)
Multivariate Gaussian Random Number Generation Targeting Reconfigurable Hardware
in ACM Transactions on Reconfigurable Technology and Systems
| Description | This research project explores novel methods and tools for hardware acceleration of financial computation in general, and for Monte Carlo simulation of financial models in particular. Our aim is to exploit the latest software and hardware technologies, particularly those based on advanced reconfigurable hardware such as FPGAs (Field-Programmable Gate Arrays), and to demonstrate the effectiveness of these technologies by applying them to overcome bottlenecks in current and future large-scale financial computation. We have: 1. Developed novel hardware architectures for: (a) various financial Monte Carlo computations such as pricing Asian options and credit risk modelling; (b) option pricing based on binomial trees, explicit finite difference techniques, and quadrature methods; (c) efficient random number generation, which is critical for many financial simulation methods. 2. Explored compile-time techniques that support high-level design, including: (a) the use of a domain-specific language for reconfigurable path-based Monte Carlo simulations; (b) an approach combining syntax-directed transformation and geometric programming. 3. Investigated methods for characterising, customising and compiling hardware resources targeting high-performance computing platforms including: (a) a cluster of computers in which each node contains both an FPGA and a GPU (Graphics Processing Unit); (b) a hybrid-core system which extends a commodity instruction set by FPGA-based application-specific instructions. 4. Studied two main extensions to the proposed approach. The first concerns FPGA accelerated low-latency market data feed processing. The second, involving a collaboration with a project supported by EP/D060567/1, concerns a new FPGA architecture optimised for floating-point applications. In this new FPGA architecture, fine-grained units are used for implementing control logic and bit-oriented operations, while parameterised and reconfigurable word-based coarse-grained units incorporating word-oriented lookup tables and floating point operations are used to implement datapaths. We demonstrated that for pricing interest rate derivatives based on the BGM model, this new architecture is 19 times smaller, 3 times faster and 12 times more energy efficient than a comparable commercial FPGA device. 5. Received five awards for our publications: (a) the Best Paper Award for the paper "Multi-level customisation framework for curve based Monte Carlo financial simulations" at the 2012 International Symposium on Applied Reconfigurable Computing. (b) the Stamatis Vassiliadis Outstanding Paper Award for the paper "FPGA-Optimised Uniform Random Number Generators Using LUTs and Shift Registers" at the 2010 International Conference on Field-Programmable Logic and Applications; (c) the Stamatis Vassiliadis Outstanding Paper Award for the paper "Domain-specific FPGA: architecture and floating point applications" at the 2007 International Conference on Field-Programmable Logic and Applications; (d) the Stamatis Vassiliadis Outstanding Paper Award for the paper "Rapid estimation of power consumption for hybrid FPGAs" at the 2008 International Conference on Field-Programmable Logic and Applications; (e) the Best PhD Student Paper Award for the paper "The coarse-grained/fine-grained logic interface with embedded floating-point arithmetic units" at the 2008 Southern Programmable Logic Conference. |
| Exploitation Route | In the short term, our work is expected to benefit mainly researchers in academia and in industry engaged in financial analysis and hardware acceleration. In the medium to long term, our work is expected to produce interesting and useful results also to industry engaged in financial analysis. We believe that the proposed research will strengthen UK's position in high-performance computing, especially for financial applications; however the results of our work will also benefit many other applications, since Monte Carlo simulation is a general technique and has been used in, for instance, heat transfer and biochemical reactions. Moreover, our work will also be useful for designers of reconfigurable architectures such as FPGAs and the associated design tools, who are interested in improving the capability of their devices and tools. |
| Sectors | Digital/Communication/Information Technologies (including Software) |
| URL | http://cc.doc.ic.ac.uk/finan.html |
| Description | Celoxica Holdings Plc |
| Organisation | Celoxica |
| Country | United Kingdom |
| Sector | Private |
| Start Year | 2006 |
| Description | Cluster Technology Limited |
| Organisation | Cluster Technology |
| Country | Hong Kong |
| Sector | Private |
| Start Year | 2006 |