Device Electronics Based on nanoWires and NanoTubes

There is considerable scope for CNFETs and Si Nanowires with their capability of ballistic transport, to be introduced into standard CMOS via a hybrid technology.The main reason currently hampering the use of this technology is an absence of controlled fabrication techniques in MOS type configurations with predictable device characteristics. Adequate physical models and simulation tools are necessary to address this issue.This collaborative research involves four partners: 1) Pisa : Atomistic modelling of ballistic transport in gated structures with contacts.(2) Vienna: Effective mass approach to transport inclusive of scattering.(3) De Montfort University : Characterisation, parameter extraction and defect analysis of devices fabricated at Cambridge. The parameters will be fed into the modelling at Pisa and Vienna.(4) Cambridge University : Fabrication of devices.The overall goal of the project is to carry out a comprehensive analysis linking theory with experiment to enable some fundamental design rules for fabrication of such technologies in future.