Modelling of Carrier Transport in Ultra Thin Body Transistors
Lead Research Organisation:
Swansea University
Department Name: College of Engineering
Abstract
Aggressive scaling of the conventional metal-oxide-semiconductor field effect transistors is required by the International Technology Roadmap for Semiconductors as conventional devices will hit a limit beyond the 45 nm technology node. Novel, ultra-thin body transistors must be introduced into production in order to sustain the expected increase in device performance. Moreover, both the Silicon device body and the SiO2 dielectric have to be replaced with a higher mobility semiconductor and higher dielectric constant materials.The proposed fellowship research aims to develop a 'state-of-art' Monte Carlo device simulator which is capable of accurately modelling the low-dimensional properties of ultra-thin body transistors. The simulator will be employed to optimise the ultra-thin body architecture, to benchmark the prospective high mobility materials, and to investigate the impact of high-K dielectrics on channel mobility. It will also focus on the exploitation of different material crystal orientations in the channel. The accompanying research grant proposal aims to establish a new Monte Carlo simulation tool and enhancing the collaborators' Non-Equilibrium Green Functions simulator employed in the investigation of nanowire transistors.
Organisations
Publications
Elmessary M
(2017)
Scaling/LER study of Si GAA nanowire FET using 3D finite element Monte Carlo simulations
in Solid-State Electronics
Elmessary M
(2016)
Anisotropic Quantum Corrections for 3-D Finite-Element Monte Carlo Simulations of Nanoscale Multigate Transistors
in IEEE Transactions on Electron Devices
Espineira G
(2019)
Impact of Gate Edge Roughness Variability on FinFET and Gate-All-Around Nanowire FET
in IEEE Electron Device Letters
Garcia-Loureiro A
(2011)
Implementation of the Density Gradient Quantum Corrections for 3-D Simulations of Multigate Nanoscaled Transistors
in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Indalecio G
(2018)
Spatial Sensitivity of Silicon GAA Nanowire FETs Under Line Edge Roughness Variations
in IEEE Journal of the Electron Devices Society
Islam A
(2012)
Monte Carlo simulations of mobility in doped GaAs using self-consistent Fermi-Dirac statistics
in Semiconductor Science and Technology
| Description | I have extended my finite element Monte Carlo device simulation tools with i) new physical models (interface roughness, interface phonons, self-consisted Fermi-Dirac statistics) and ii) guided the development of a 3D real space finite element Monte Carlo device simulation code. The development of finite element 3D Monte Carlo code has been driven by the rise of non-planar transistor architectures but was, originally, planned to be done at the end of the fellowship programme. I have also developed a multi-subband 2D real space Monte Carlo device code but it use turned to be limited due to the appearance of multi-gate, non-planar 3D transistor architectures. I have achieved practically all 6 objectives which were: 1. Replacement of the 3D k-space electron transport model in the MC simulator with a quasi-2D k-space transport model in an energy minimum valley whilst the electron transport in all other valleys will be treated in 3D k-space; Result: The new Monte Carlo device code using a multi-subband transport model has been developed for III-V semiconductor devices. 2. Introduction of relevant scattering mechanisms including improved interface roughness scattering, remote Coulomb scattering, electron scattering with the image charges, electron-soft-polar interface optical phonon interactions, and electron-electron scattering. Result: The new electron scattering models have been included for interface roughness, remote Coulomb interaction (turned to be negligible), electron-interface phonons. I have not been able to achieve only one item in this objective to include the electron-electron scattering (which also includes electron scattering with the image charges). Unfortunately, it has turned to be too time consuming for the five year research programme. However, plans are drawn to carry out this development with one of my new PhD students. 3. Replacement of the analytical non-parabolic band structure model currently adopted in MC device simulations with tight-binding band structure calculations for all channel materials of interest. Result: This objective has been dropped in the favour of the objective 4. 4. Introduction of flexible device topology into the existing MC simulator with a 2D real-space mesh and development of a 3D real-space version capable of handling the complex geometry of the novel devices. Result: A parallel 3D finite element Monte Carlo device code has been developed using quantum corrections (density gradient approach) and interface roughness scattering. Theoretical issues related to finite element meshes in ensemble Monte Carlo device simulations have been tackled in a novel approach. The code has been usefully tested against experimental data of 25nm gate length Si SOI FinFET achieving an excellent agreement. This served for intensive study of carrier transport in the device. 5. Incorporation of carrier scattering and new materials into the NEGF device simulator for the investigation of nanowire transistors. Result: This was done in collaboration with Antonio Martinez as planned. 6. Extensive study of transport phenomena in the novel devices with new materials and different channel orientations understanding the interplay between density of states, effective masses, injection velocities, 2D scattering and their impact on ballisticity and drive current. Result: The previously described Monte Carlo and NEGF codes have been used in many EPSRC and EU FP7 projects to study various version of thin-body transistors based on Si and III-V semiconductors resulting in numerous publications, see the list of publications. 7. Identification the most attractive UTB device architectures for the future generations of CMOS devices on optimisation of the device design in terms of device geometries and material combinations. Result: This has been done, identifying an InGaAs as the optimal channel material for III-V MOSFETs and identifying FinFET and nanowire device architectures as the most promising solutions for future digital technology. Note that the prediction of the FinFET architecture has been confirmed by the Intel's announcement that TriGate MOSFETs (a variant of FinFET) will be used in mass production for the 22 nm technology node from December 2011. |
| Exploitation Route | Design of transistor architectures till the end of semiconductor devices roadmap. |
| Sectors | Digital/Communication/Information Technologies (including Software),Electronics |
| URL | http://engweb.swan.ac.uk/~karolkalna/III-VMOSFETgrant.html |
| Description | The work from the 5-year research gives a deep in-sight into ultimate scaling of Si and InGaAs MOSFETs to a gate length of 5 nm. The work demonstrates that we remain our world-leading position in R&D of III-V MOSFETs for future digital applications. In addition, a novel state-of-the-art 3D finite element ensemble Monte Carlo incorporating 2D Schroedinger Equation quantum corrections simulation toolbox was developed and intensively employed to study performance and variability of multi-gate non-planar transistor architectures (FinFETs, nanowire FETs, nanosheet FETs). In particular, these simulation tools help to determine issues degrading performance of transistors when scaled to ultimate dimensions and suggests ways to optimise their design in industrial R&D. They also point to sources of transport degradation in planar transistors thus justifying the change of transistor architecture to non-planar. |
| First Year Of Impact | 2007 |
| Sector | Digital/Communication/Information Technologies (including Software),Electronics,Energy |
| Impact Types | Societal,Economic,Policy & public services |