Germanium Manufacturing on Sapphire/Alumina (GEMS)

The rapid advances in integrated circuits over recent decades have mainly been achieved through scaling of CMOS transistor dimensions. Future advances will require the application of new structures and new materials such as strained silicon and SiGe on insulator technology. The thickness of the silicon dioxide transistor gate dielectric cannot be reduced any further due to high tunnelling currents. If this is not to be a hindrance to scaling then the gate dielectric will need to be replaced with a material of higher permittivity (high k ). In that case germanium becomes a very attractive and competitive material for advanced CMOS technology. Germanium has a high carrier mobility and is also lattice matched to GaAs thus enabling the coupling of electronics and photonics. A drawback of silicon on insulator (SOI) and future germanium on insulator (GeOI) substrates is that the Buried silicon diOXide (BOX) layer is a good thermal insulator making heat removal a problem. This can be overcome with germanium on sapphire (GeOS) technology. Sapphire has a good thermal conductance, is an excellent substrate for minimising RF losses and has a temperature coefficient of expansion nearly matched with germanium.The main disadvantage of germanium is that junction leakage currents are high. However, fully depleted CMOS devices require ultra thin semiconductor layers, thus junction leakage will be minimised. Fully depleted transistors on GeOS will require a good electrical interface between the germanium and the buried dielectric. Thus it is proposed to employ a thin germanium oxynitride and/or deposited alumina layer between the sapphire and the germanium.This project will establish a technology for the fabrication of thin GeOS substrates, will characterise the quality of the germanium layer and the interface with the buried dielectric, and will determine the thermal conductivity of the structure.