Multiscale Modelling of Metal-Semiconductor Contacts for the Next Generation of Nanoscale Transistors

Contacts, made up of metal-semiconductor interfaces, are integral parts any semiconductor device. Compatibility of the metal and semiconductor components, homogeneity of structural and electrical characteristics of their interfaces, and robustness and durability of the contacts are crucial for the device proper functionality.Optimal operation of the contacts is a key to realisation of novel devices and development of new device concepts, including high mobility semiconductors based CMOS, tunnelling and spin-based transistors, tunnelling diodes, gas and infrared carbon-nanotube detectors, etc. Two major current trends in the semiconductor industry - miniaturisation of the devices and shift to new materials - pose the challenges for the contact technology: (i) robustness and stability of operation in ever smaller devices and (ii) compatibility of metal and semiconductor components. For example, the resistance of present day contacts is strongly affected by fluctuations in the currently being developed sub-22 nm technology. This problem is getting worse for smaller devices. On the other hand, introduction of new materials for high-mobility channels, e.g., Ge and III-Vs, necessitates the search for compatible metals and brings new challenges related to the contact fabrication. Therefore, understanding the dependence of the nanoscale metal-semiconductor interface properties on the atomic structure of this interface, chemical composition disorder, and defects is a key to formulating and exploiting new device concepts. In particular, this understanding is imperative for the developing of optimal contact fabrication procedures for nano-scale semiconductor devices.Primary aims of the proposed research are i) enabling and carrying out multiscale modelling of the optimal chemical compositions and structures of metal-semiconductor interfaces such that the Schottky barrier is minimal;ii) analysis of the role of interface defects, strain, and disorder on the carrier transport in CMOS devices.We will first develop a methodology which bridges ab initio simulations of atomic-scale structures and electronic properties of interfaces at 1-3 nm scale and simulation of device current-voltage characteristics at the scale of 5-50 nm. The results of the ab initio calculations will be transferred into 3D Monte Carlo (MC) transport simulations, which will allow us to make a realistic representation of the metal-semiconductor interface and develop a physical model of source/drain contacts. This model, in turn, will be incorporated into a 2D MC device simulator to predict the device performance and thus allow one for the straightforward comparison with experimental data obtained directly from the operating devices. Such methodology will allow us: i) to consider explicitly effects of point defects (<0.5 nm scale), composition disorder (~1 nm scale), and metal granularity (~1-2 nm scale) on the electronic properties of selected metal-semiconductor interfaces, ii) to incorporate these effects into 3D MC transport simulations through the metal-semiconductor interfaces,iii) to develop realistic models for source/drain contacts, carry out 2D MC device simulations, and to optimise device performance with respect to the properties of the contacts.The methodology will be first tested on the case of Ti metal contact with an archetypal III-V semiconductor GaAs and the results will be validated using experimental data provided by our project partners. Then other systems of increasing complexity will be investigated: interfaces of Ti metal with unary Si and Ge, doped GaAs, and ternary InGaAs semiconductors and, finally, interfaces of TiN metal alloy with InGaAs. Our theoretical predictions will be validated by and compared to experimental results at each scale: Transmission Electron Microscopy (TEM) data for the interface structures, resistance measurements for the transport through the interface, I-V characteristics for the device simulations.

This proposal on metal-semiconductor contact modelling aims to bring a large benefit to many nano-scale semiconductor device concepts thus spanning from the enabling future solutions for semiconductor industry to the research into novel devices in academia and industry. Low resistance contacts, which are the ultimate outcome of the proposed research, are crucial for the performance or even functionality of many advanced nano-electronics devices and novel device concepts. The developed methodology and simulation tools will decisively help to understand how the metal-semiconductor contact works in nano-scale dimensions enabling to tailor the contact solutions for a particular device. In order to maximise the impact, we have selected a particular metal on III-V semiconductor which is of the paramount importance to our collaborators for future device solutions beyond the 22 nm technology for digital applications. This selection originates from the fact that the access contact resistance is a major limiting factor to the device performance based on high mobility materials like III-Vs or Ge in currently developed sub-22 nm technology. The project is vitally supported via the collaborations with IMEC (M. Meuris), the largest European semiconductor research centre; with TSMC (M. Passlack and G. Doornbos), the World's largest semiconductor foundry; and with IBM (W. Haensch) thus clearly establishing the communication lines. We are planning to held regular annual meetings with these collaborators. We will also prepare annual reports of our research activities and essential results that will be send to the industrial partners and then critically assessed. The developed methodology and simulation tools is planned to be exploited in many ways. It is envisaged that our primary collaborators TSMC and IBM as well as industrial partners in the internal III-V MOSFET project of IMEC like STMicroelectonics and AMD will use the developed methodology in their products. Note here that the industry will apply the developed methodology not just to III-V based transistors but to every other nano-scale device aimed for market. If successful, we will aim for a commercial exploitation by patenting the methodology and tools that will be assisted by Department of Research & Innovation at Swansea, and UCL Business at UCL. The UK industry related to electronic technologies like ARM, Cambridge Silicon Radio, and picoChip will also profit in many ways from this research. For example, since ARM is routinely developing products for STMicroelectonics (Cortex-M), the project will help ARM to sustain and may be even improve its position on the market. In addition, we will explore a possibility to offer our developed methodology and simulation tools to material and device simulation companies like Accelrys and QuantumWise.