High permittivity dielectrics on Ge for end of Roadmap application
Lead Research Organisation:
Liverpool John Moores University
Department Name: Engineering Tech and Maritime Operations
Abstract
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Publications
Baojun Tang
(2014)
Experimental Evidence Toward Understanding Charge Pumping Signals in 3-D Devices With Poly-Si Channel
in IEEE Transactions on Electron Devices
Baojun Tang
(2012)
Investigation of Abnormal $V_{\rm TH}/V_{\rm FB}$ Shifts Under Operating Conditions in Flash Memory Cells With $ \hbox{Al}_{2}\hbox{O}_{3}$ High-$\kappa$ Gate Stacks
in IEEE Transactions on Electron Devices
Baojun Tang
(2014)
Evaluation and Solutions for P/E Window Instability Induced by Electron Trapping in High-<inline-formula> <tex-math notation="TeX">$\kappa$ </tex-math></inline-formula> Intergate Dielectrics of Flash Memory Cells
in IEEE Transactions on Electron Devices
Benbakhti B
(2012)
Characterization of Electron Traps in Si-Capped Ge MOSFETs With $\hbox{HfO}_{2}/\hbox{SiO}_{2}$ Gate Stack
in IEEE Electron Device Letters
Duan M
(2012)
Defect Loss: A New Concept for Reliability of MOSFETs
in IEEE Electron Device Letters
Duan M
(2013)
New Analysis Method for Time-Dependent Device-To-Device Variation Accounting for Within-Device Fluctuation
in IEEE Transactions on Electron Devices
Duan M
(2013)
Defect Losses under Different Processes, Stress, Recovery, and Anneal Conditions
in ECS Transactions
Duan M
(2014)
Development of a Technique for Characterizing Bias Temperature Instability-Induced Device-to-Device Variation at SRAM-Relevant Conditions
in IEEE Transactions on Electron Devices
Duan M
(2013)
Key issues and techniques for characterizing Time-dependent Device-to-Device Variation of
in Technical Digest of the International Electron Devices Meeting (IEDM)
Duan, M.
(2013)
Key issues and techniques for characterizing Time-dependent Device-to-Device Variation of SRAM
in 2013 Ieee International Electron Devices Meeting (Iedm)
| Description | The key findings of this project upto now include: (1) The capture cross sections of electron traps are determined; (2) An energy switching model has been proposed for hole traps; (3) The energy profile of hole traps has been extracted; (4) Mechanism for the differences in NBTI under DC and AC stresses has been clarified; (5) The sources for defects have been identified. (6) Based on the above, a technique for predicting the BTI lifetime under both DC and AC stresses has been proposed and testified against experimental data. |
| Exploitation Route | Potential use includes: (i) Assess the PBTI device lifetime under both DC and AC stresses for Ge nMOSFETs; (ii) Assess the NBTI device lifetime under both DC and AC stresses for Ge pMOSFETs; (iii) Process optimization by suppressing defects through controlling the identified sources. (iv) Modelling the device degradation in circuits using Ge MOSFETs. Exploitation routes are: (i) Non-academic project partners; (ii) International conferences. |
| Sectors | Digital/Communication/Information Technologies (including Software),Education,Electronics |
| Description | 1. The BTI lifetime prediction method has been used in the qualification of the Ge processes. 2. The sources of defects identified have been used in assisting process optimization. 3. The PI has been invited to deliver short courses on Bias Temperature Instability modelling. |
| First Year Of Impact | 2019 |
| Sector | Digital/Communication/Information Technologies (including Software),Education,Electronics |
| Impact Types | Economic |