Yield and reliability enhancement techniques for novel memory devices

Describe the proposed research in simple terms in a way that could be publicised to a general audience [up to 4000 chars]. Note that this summary will be automatically published on EPSRC's website in the event that a grant is awarded.

The recently developed memory architectures based on resistive-variable devices such as Phase Charge Memories, Programmable Metallization Cell or memristors have reliability issues that are drastically different from those affecting CMOS based memories. These novel memories although based on different technologies, they all share the principle of storing information as the resistance value imposed to a resistive-variable devices and consequently also the possible type of faults that may occur.
This project proposes to leverage data obtained from experimental results to characterize resistive-variable devices and to exploit both information and architectural redundancies to enhance reliability and yield of these devices.
To face the presence of a massive number of defects suitable spare resources, such as spare row and/or columns will be used combined with suitable error detection methods and efficient readdressing scheme to substitute faulty elements. To leverage the use of spares resources, codes novel models and algorithms to estimate the reliability versus overhead trade-off will be developed, with the aim of obtaining a reliability-aware driven synthesis tool for these memory devices.

The project "Yield and reliability enhancement techniques for novel memory devices" addresses a challenging topic of current trend in design and manufacturing of electronic devices.
The introduction of novel devices for designing high density, low power, non-volatile memories is one of the upcoming major technological innovations, however together with this innovation it will be required a deep rethinking with respect to yield and reliability issues due to the high defect rate and the new kind of faults that affect devices based on these technologies.

The main beneficiaries of this research will therefore be industry, both manufacturing and software houses providing tools for Computer-Aided Design. The former will be able to produce memory devices with impressive memory capacity and extraordinary characteristics in terms of power consumption starting from devices so small that are very prone to faults. The latter will be able to provide design flow and CAD tools that are reliability-aware, and that enable the design of circuits based on totally different technology paradigms.

Industrial beneficiaries who have expressed interest to use the project results immediately through collaborative links include:

Intel: The main microprocessor manufacturer considers the development of novel technologies for memory manufacturing crucial for achieving performance scalability for emerging applications and workloads (see support letter from Dr. Priyadarsan Patra).
HP: The first company that developed memristor in its research labs supports our proposal and considers that its success will significantly advance the area of memory design and computing (see letter from Dr. Prith Banerjee)
ST Microelectronics: The largest European based semiconductor company expressed strong interest in our proposal.

The impact of a positive result of the proposed activity will eventually affect the final users who will be able to benefit from continuous improvement of the performances and low power of consumer devices.