A higher-order approach to codesign - 27659

Current computing architectures are moving increasingly towards
heterogeneity, as physical limitations of scale demand a
bifurcation of optimisation techniques between reducing latency and
increasing throughput. In the past, the amount of heterogeneity in
devices tended to be limited, therefore RTL were largely suitable for for
hardware design. However, recently there has been a surge
of industrial interest in hybrid programmable hardware-software systems.
For example, Xilinx has recently launched the
Zynq platform which combines a multicore ARM processor with programmable
logic. This development thrusts the question
of design for such hybrid systems, requiring different programming
methodologies, into the foreground.

In general, as architectures move away from the conventional CPU and RAM
(von Neumann) model, the task of devising
programming models for them falls mostly with their designers, who are
usually engineers rather than programming
language experts. As a result we are witnessing a flurry of
architecture-specific languages (ASL), reminiscent of the early
days of computation when each computer came with its own operating system,
programming language, etc. Whereas ASLs
are unavoidable, good programming methodology recommends that they should
be used primarily for the development of
system-level infrastructure. The application-level, algorithmic
programming should happen as much as possible in portable,
machine-independent languages. These lessons are very well known in the
programming community and this knowledge
can be profitably used in electronic design. We aim to address this
problem.

The challenge of heterogeneous codesign is both quantitative and
qualitative. A program has components that must be
compiled into the FPGA fabric and others to be compiled for the CPU. The
reasons are either efficiency (certain
architectures are better at running certain types or code) or physical
constraints (interactions with other components in a
complex design, availability of IP cores, drivers or libraries). But a
program may also have components which can be
compiled to either architecture or both. A choice must be made and it is
reasonable for this choice to be also motivated by
efficiency.

In this proposal we will combine and unify the way type systems in
higher-level languages specify and solve qualitative
(hard) constraints with quantitative optimisation techniques.
Specifically, we will investigate the optimization of memory
subsystems to support parallel access, by combining knowledge of memory
access patterns from the code, resulting in
highly efficient programmable memory controllers. In addition, we will
optimize the allocation of precision within a combined
hardware/software system in order to achieve an accuracy specification
while taking into account the capability and cost
implications of the programmable hardware and native data types supported
in the software. This combined approach can
work both at the source code level (program transformations motivated by
underlying cost models) and at the synthesisedmachine code and HDL level
(pipelined optimisations, etc). We will use a "game semantic" model,
already successfully
applied to hardware synthesis from higher order languages, to establish
the correctness properties of the type system and
to drive the compilation process.

This proposal will result in scientific advances and new techniques in line with the proposed project aims of each WP (heterogeneous compilation, heterogeneous optimisation, advanced cost models, automated partitioning). We plan three routes to ensure the impact of these advances. Firstly, the traditional academic dissemination route is discussed; this route is also of vital importance outside the academic environment: UK and international applied research labs and companies often pick up on publications in the high-quality conferences and journals where we intend to disseminate our work as the starting point to apply fundamental results. Secondly, we plan to release our tools and techniques developed on the web. Thirdly, we will train (in house and through summer schools) three young researchers in a unique combination of advanced skills and deep knowledge at the systemic interface between hardware and software. A proposal with such deep and wide-ranging implications has the potential to generate significant interest in the general public and general interest science and technology press, if presented appropriately.

Within the central research area covered by this proposal, higher level methods for codesign, there is a very timely opportunity for the UK economy. As noted in the case for support, it is currently very unclear how to derive both convenient abstractions and good performance from heterogeneous hardware. This uncertainty opens a major opportunity for the UK to regain a leading role in the industry, with the potential to produce both deep fundamental insights and the potential to repeat UK economic success stories such as ARM.