Multisphere: Consistently Parallelizing High-Dimensional Sphere Decoders

During the last decades, the evolution of wireless and mobile communication systems has significantly contributed to the economic and social improvement of both developed and developing countries and it has transformed the daily lives of millions of people. Our increasing need to connect to anything (from people to services and physical things) at any time and to access/exchange increasing amounts of information despite the existing limitations in the available frequency spectrum and processing capabilities, as well as our need to experience "zero-latency" wireless access, has imposed the need to revisit the way communication systems are designed.

Targeting pragmatic future wireless systems able to deliver the capacity scaling predicted in theory, the proposed research focuses on two, currently in progress, paradigm shifts that have a strong potential to transform the way we design wireless communications systems: (a) The one from orthogonal to non-orthogonal signal transmissions according to which instead of trying to prevent transmitting signals from interfering, we now intentionally allow mutually interfering information streams, and (b) the one from sequential to parallel (receiver) processing according to which instead of using one processing element to perform the calculations of a functionality, we now split the corresponding processing load onto several processing units. While digital processing systems with tens or even hundreds of processing elements have been predicted, it is still not obvious how we can efficiently exploit this processing power to develop high-throughput and power efficient wireless communication systems, and specifically how we can cope with the exponentially computationally intensive case of optimally recovering a large number of (intentionally) interfering information streams.

This research targets a theoretical and practical framework for efficiently parallelizing sphere decoders used to optimally reconstruct a large number of mutually interfering information streams. Sphere decoding is a well-known technique that dramatically reduces the related complexity. However, while sphere decoding is simpler, compared to other solutions that are able to deliver optimal performance, its complexity still increases exponentially with the number of interfering streams, preventing the practical throughput gains from being scaled by increasing the number of mutually interfering streams as predicted in theory. This research targets practical sphere decoders able to support a large number of interfering streams with processing latency or power consumption requirements which are orders of magnitude smaller than those of single processor systems.

The research addresses the key EPSRC priority "Many-Core-Architecture and Concurrency in Distributed and Embedded Systems" and will contribute to the design and implementation of future wireless communication systems by enhancing our understanding of the theoretical and practical aspects related to the development of parallel processing architectures for wireless communication systems and by introducing a framework for related implementation decisions.

The evolution of wireless and mobile communication technologies can transform the way we live and work. Investing in the information economy has been recognized by the UK as a way to contribute to a strong sustainable growth and according to the "Information Economy Strategy" (June 2013) "we want the next generation of mobile technology to be developed here in the UK". This research contributes to this vision and addresses the key EPSRC priority "Many-Core-Architecture and Concurrency in Distributed and Embedded Systems", by contributing to the theory, design and development of technologies able to scale to the capacity of future wireless communication systems despite the current limitations in frequency spectrum and (single) processors' speed.

Results of this research will act as enablers of the next generation of wireless communication technologies (e.g., 5G) and will contribute to an enhanced wireless infrastructure which is vitally important for the digital economy and for all the UK business and society. In addition, the research will contribute to UK's academic standing in the field for wireless communications and signal processing, and to the training of highly skilled researchers and engineers who will be exposed to theory and practice of several disciplines (i.e., with elements from communication systems, digital systems design and computer science).

In addition, since the proposed research addresses the design and implementation of advanced digital systems (e.g., design of Many-Processor on Chip - MPSoC) for wireless and mobile communication systems it can directly impact telecommunications equipment makers (e.g., Huawei, Samsung), semiconductor and system-on-chip manufacturers (e.g., ARM Holdings, NVIDIA) companies who produce embedded hardware and software for wireless communication systems (e.g., Freescale Semiconductor) as well as manufacturers of test equipment (e.g., Aircom, Rhode and Schwarz).