Autonomous NAnotech GRAph Memory (ANAGRAM)

Artificial intelligence (AI) is transforming our societies, but the more it proliferates, the higher the customer demands for functionality and efficiency (most notably energy). Thus, as time progresses the limitations of statistical learning-based AI that has underpinned most AI work so far are beginning to naturally become more exposed. Tasks such as variable binding and manipulation, inductive reasoning and 1-shot learning, at which statistical learning is not as strong, suggest solutions in the sphere of abstract symbol processing AI. The commonly referenced 'next wave of AI' that is capable of such exploits (towards "strong AI") is likely to make extensive use of symbol processing capabilities and simultaneously demand a bespoke set of hardware solutions. The proposed project primarily addresses the issue of developing general-purpose (platform-level) hardware for precisely symbolic AI.

The proposed project seeks to develop a memory module that features: a) an internal structure and b) in-memory computing capabilities that render it particularly suitable for symbolic processing-based artificial intelligence (AI) systems. Ultimately the project seeks to deliver: 1) Two microchip iterations prototyping the memory system. 2) A software environment (infrastructure) for easy programming and operation of the resulting microchips (includes simulation capabilities for proof-of-concept tests). 3) A demonstration of the memory cell operating together with a symbolic processor as an aggregate system. 4) A functioning set of starter applications illustrating the capabilities of the design.

The overall effort is driven by a philosophy of co-optimising the memory across the entire trio of fundamental device components, symbolic AI mechanics and hardware design facets. Specifically: functionality in the proposed memory system will be pursued by: a) Designing a resistive RAM-based (ReRAM) memory unit where operation of the ReRAM devices and ReRAM tech specifications themselves are subservient to the specific operational goals of the memory system. b) Adapting the mathematical machinery of the system in order to map functional operations to hardware-friendly machine-code level operations: the stress is on hardware-friendliness, not mathematical elegance. This will be inextricably linked to the design of the memory's instruction set. c) Designing an architecture that runs the symbolic memory efficiently by using memory allocation techniques that maximise locality and making extensive use of power-gating. Simultaneously, implementation of a solid software stack infrastructure will enable efficient and fast prototyping and hypothesis testing.

The cornerstone of the targeted project impact is to lay the foundations for launching an industrial-scale design effort towards hardware for symbolic AI. Hence the bulk of the effort is in chip design (prototype-based de-risking of the idea) and toolchain development (impact acceleration by lowering barriers to user uptake). Simultaneously, it is expected that the project will play a significant role in enhancing interest in symbol-level AI and very crucially, inducing interest in connecting symbolic AI with statistical learning one; thereby significant impact on knowledge is achieved. Finally, the increased in the capabilities of AI, as well as the transparency of decision-making (typically readily expressible via formal expressions or even in pseudo-natural language) offered by the symbolic approach promise to make a significant impact in enhancing acceptance of AI by society, providing a solid scientific foundation for certification processes (AI trust - broadening the scope of applications that accept an AI solution). With hardware available for this task, significant impact on productivity and quality of life is to be achieved.

The project is self-contained and is designed to launch a much broader, sustainable effort, headed by the PI in this field.