Platform: Strained Si / SiGe: Materials, Technology and Design
Lead Research Organisation:
Newcastle University
Department Name: Electrical, Electronic & Computer Eng
Abstract
This Platform Grant will sustain research being carried out at Newcastle University in strained Si/SiGe materials, technology and design. EPSRC, EC and industrial funding has been continuous in this field since 1994, resulting in the publication of more than 50 papers. The world market for semiconductors is counted in $100 Billion's per year and new innovations are now necessary to deliver the raw processing power needed to maintain Moore's Law in the future. Strained Si/SiGe CMOS technology has been pursued to meet this challenge. A thick layer of SiGe deposited on a Si wafer, so that it is relaxed, forms a virtual substrate. A thin layer of Si grown subsequently on the virtual substrate becomes tensile strained, while SiGe epitaxial layers may be either compressive (if the Ge content is above that of the virtual substrate) or tensile (if the Ge content is below that of the virtual substrate). The higher carrier mobility seen in strained Si/SiGe devices can be exploited through higher speed (without re-tooling), larger fan-out or lower power. Our long-term goal is to build an international centre of excellence in the area of synergy between new materials, devices and system design. Specific topics include: material growth, critical thickness, diffusion, defects, device scaling, strain budget design, MOSFET gate stacks, device and process modelling, electrical characterisation, strain characterisation, doping characterisation, robust design and variability in technology-driven design of circuits.
Organisations
Publications
Yan L
(2009)
1/f noise study on strained Si0.8Ge0.2 p-channel MOSFETs with high-k/poly Si gate stack
in Solid-State Electronics
Fiegna C
(2008)
Analysis of Self-Heating Effects in Ultrathin-Body SOI MOSFETs by Device Simulation
in IEEE Transactions on Electron Devices
Escobedo-Cousin E
(2009)
Defect identification in strained Si/SiGe heterolayers for device applications
in Journal of Physics D: Applied Physics
Agaiby R
(2010)
Direct Measurement of MOSFET Channel Strain by Means of Backside Etching and Raman Spectroscopy on Long-Channel Devices
in IEEE Electron Device Letters
Alatise O
(2009)
Improved Analog Performance in Strained-Si MOSFETs Using the Thickness of the Silicon–Germanium Strain-Relaxed Buffer as a Design Parameter
in IEEE Transactions on Electron Devices
Alatise O
(2010)
Improved self-gain in deep submicrometer strained silicon-germanium pMOSFETs with HfSiO /TiSiN gate stacks
in Microelectronic Engineering
Alatise O
(2010)
Linearity and mobility degradation in strained Si MOSFETs with thin gate dielectrics
in Solid-State Electronics
Fjer M
(2011)
Low Frequency Noise in Strained Si Heterojunction Bipolar Transistors
in IEEE Transactions on Electron Devices
Alatise O
(2009)
Performance Enhancements in Scaled Strained-SiGe pMOSFETs With $ \hbox{HfSiO}_{x}/\hbox{TiSiN}$ Gate Stacks
in IEEE Transactions on Electron Devices
Persson S
(2010)
Strained-Silicon Heterojunction Bipolar Transistor
in IEEE Transactions on Electron Devices
Alatise O
(2010)
The impact of self-heating and SiGe strain-relaxed buffer thickness on the analog performance of strained Si nMOSFETs
in Solid-State Electronics
Description | The piezoresistance model has commonly been used to describe mobility enhancement for low levels of process induced strain in CMOS technology. However, many reports show it failing to describe the superlinear behavior observed at high levels of stress. This is because the approximation made is only valid for very low stress levels. A conversion between the change in conductivity and resistivity is developed such that a piezoresistance model can be applied correctly to calculate the strain-induced mobility changes. Hence, the overall accuracy is improved compared to the conventional formulation. Measuring strain in long-channel MOSFETs on silicon-on-insulator (SOI) and strained-SOI platforms is demonstrated using ultraviolet (UV) Raman spectroscopy. Removal of the Raman inactive strain-inducing metallization layers is avoided by etching trenches under transistors without mask alignment in order to expose the channel region. The technique is shown to be repeatable and does not alter the initial strain state in the channel. Nanometer-scale strain resolution is demonstrated using conventional Raman spectroscopy to profile strain through thin epitaxial Si/SiGe layers used as high mobility metal oxide field effect transistor channels. Thin strain relaxed buffer (SRB) devices are shown to offer the same performance enhancements as thick SRB devices. The reduction in performance enhancement with device scaling widely reported in the literature has also been investigated. Correcting for dynamic self-heating effects using ac measurements, the enhancements seen in long channel devices are maintained down to short channel lengths, demonstrating the scalability of SRB technology. |
Sectors | Electronics |
Description | CPI Ltd |
Amount | £114,776 (GBP) |
Organisation | Centre for Process Innovation (CPI) |
Sector | Private |
Country | United Kingdom |
Start |
Description | CPI Ltd |
Amount | £114,776 (GBP) |
Organisation | Centre for Process Innovation (CPI) |
Sector | Private |
Country | United Kingdom |
Start |
Description | EPSRC |
Amount | £528,499 (GBP) |
Funding ID | EP/H023666/1 |
Organisation | Engineering and Physical Sciences Research Council (EPSRC) |
Sector | Public |
Country | United Kingdom |
Start |
Description | Leverhulme Trust |
Amount | £32,900 (GBP) |
Funding ID | F001254AG |
Organisation | The Leverhulme Trust |
Sector | Charity/Non Profit |
Country | United Kingdom |
Start |
Description | Leverhulme Trust |
Amount | £32,900 (GBP) |
Funding ID | F001254AG |
Organisation | The Leverhulme Trust |
Sector | Charity/Non Profit |
Country | United Kingdom |
Start |